Samsung Electronics Co., Ltd.

Jonghyuk Kim

Hyoseok Na

Soon-Moon Jung

Han-Soo Kim

Wonseok Cho

Bok-Yeon Won

Min-Sung Song

YoungSeop Rah

Jang Young Chul

Seung-jun Lee

Jaehee Kim

Dongryul Shin

Joonsoo Park

Sang-yun Kim

Donggeon Kim

SoonMok Ha

Woosung Choi

Sangdeok Lee

Selyung Yoon

A semiconductor memory device includes a memory bank arranged into first through nth split regions containing at least one memory cell sub-array within each split region, and first through nth global input/output (GIO) split lines electrically coupled to the first through nth split regions. First through n-lth connection control transistors are provided, which have gate terminals responsive to respective connection control signals. The first connection control transistor is configured to electrically short the first and second GIO split lines together when enabled by a corresponding connection control signal, and the n−1th connection control transistor is configured to electrically short the n−1th and nth GIO split lines together when enabled by a corresponding connection control signal. A GIO sense amplifier is provided, which is electrically coupled to the memory bank. A control circuit is provided, which is configured to reduce I/O signal line power consumption within the memory device during read (and write) operations.

Semiconductor memory devices having adjustable I/O signal line loading that supports reduced power consumption during read and write operations

A bit line sense amplifier of a semiconductor memory device includes: sense amplifier blocks including a PMOS driver or an NMOS driver that detects and amplifies a signal difference between a bit line and a complimentary bit line, and sequentially arranged in a bit line extending direction; column selection units that connect the bit line and a local input/output line according to a first column selection signal; complimentary column selection units that connect the complimentary bit line and a complimentary local input/output line according to a second column selection signal; column selection lines that transmit the first column selection signal to each of the column selection units; and complimentary column selection lines that transmit the second column selection signal to each of the complimentary column selection units. The column selection units and the complimentary column selection units may be disposed to be distributed between the sense amplifier blocks.

Bit line sense amplifier of semiconductor memory device and semiconductor memory device having the same

Various embodiments of the present disclosure relate to a package structure capable of allowing a shield used for noise attenuation to be used for other purposes, in an electronic device in which components are arranged at high density, and an operation method for preventing/reducing noise radiation or detecting in advance defects in a manufacturing process using the same. For this, an electronic device may include: a printed circuit board (PCB), and a package disposed on the printed circuit board. The package may include: a ground pad and at least one shield pad connected to the printed circuit board, a laminated structure comprising a plurality of laminated ground layers electrically connected to the ground pad by at least one via hole, at least one electronic component disposed on an uppermost surface of the plurality of laminated ground layers, a shield covering the at least one electronic component, wherein the at least one component is not exposed to the outside, and at least one switch device comprising a switch including a first terminal electrically connected to the shield through a first conductor wiring, a second terminal electrically connected to one of the plurality of ground layers through a second conductor wiring, and a third terminal electrically connected to the shield pad through a third conductor wiring and disposed on the uppermost surface and configured to selectively connect the first terminal to the second terminal or the third terminal wherein the shield is connected to one of the one ground layer or the shield pad.

Shield structure in electronic device and operation method thereof

An embodiment of the disclosure provides a tunable radio frequency (RF) circuit, a control method, and an electronic device including the same. An electronic device according to an embodiment of the disclosure may include an antenna, a transceiver, a tunable radio frequency (RF), and at least one processor operatively coupled with the transceiver and the tunable RF circuit. The tunable RF circuit may further include a switch, a low noise amplifier (LNA), a power amplifier (PA), a fixed filter configured to pass signals in a first frequency band, and attenuate signals in a second frequency band at least one tunable filter configured to pass signals in at least a portion of the second frequency band, where the portion of the second frequency band is tunable, and at least one detector configured to detect a signal strength passing through the at least one tunable filter.

Tunable radio frequency circuit, control method and electronic device including the same

An electronic device is provided. The electronic device may include a printed circuit board (PCB) having a ground, an antenna, a communication circuit electrically connected to the antenna through a first feeding line, a sensor module electrically connected to the antenna through a second feeding line, a first capacitor disposed on a shorting line connecting the antenna and the ground, and having a first capacitance, a second capacitor disposed on the shorting line and having a second capacitance, and a frequency-selective circuit disposed on the shorting line and selectively delivering a signal to the first capacitor or the second capacitor.

Electronic device including frequency-selective circuit connected to antenna and control method thereof

A method for manufacturing a semiconductor device includes forming first and second lower structures including selection elements on first and second chip regions of a substrate, respectively, forming first and second mold layers on the first and second lower structures, respectively, forming first and second support layers on the first and second mold layers, respectively, patterning the first support layer and the first mold layer to form first holes exposing the first lower structure, forming first lower electrodes in the first holes, forming a support pattern including at least one opening by selectively patterning the first support layer while leaving the second support layer, and removing the first mold layer through the opening. A top surface of the support pattern is disposed at a substantially same level as a top surface of the second support layer.

Semiconductor devices and methods for manufacturing the same

In multiple-layered memory devices, memory systems employing the same, and methods of forming such devices, a second memory device layer on a first memory device layer comprises a second substrate including a second memory cell region. The second substrate includes only a single well in the second memory cell region, the single well of the second memory cell region comprising a semiconducting material doped with impurity of one of a first type and second type. The single well defines an active region in the second memory cell region of the second substrate. Multiple second cell strings are arranged on the second substrate in the second active region. Although the second memory cell region includes only a single well, during a programming or erase operation of the memory cells of the second layer, requiring a high voltage to be applied to the single well in the substrate of the second layer, the high voltage will not interfere with the operation of the peripheral transistors of the first layer, second layer, or other layers, since they are isolated from each other. As a result, the substrate of the second layer can be prepared to have a thinner profile, and with fewer processing steps, resulting in devices with higher-density, greater reliability, and reduced fabrication costs.

Growing community of inventors

Gyeonggi-do, South Korea

Jonghyuk Kim