Toshiba Memory Corporation

Samsung Electronics Co., Ltd.

Jonghyeon Kim

Hyoun Kwon Jeong

Julien Margetts

David Malcolm Symons

Paul Edward Hanham

Francesco Giorgio

Kang Seok Seo

Senthilkumar Diraviam

Soogil Jeong

Provided is a method for performing computations near memory, the method including receiving, at a processor core of a storage device, a request to perform a first function on first data, the first function including a first operation and a second operation, performing, by a first processor-core acceleration engine of the storage device, the first operation on the first data, based on first processor-core custom instructions, to generate first result data, and performing, by a first co-processor acceleration engine of the storage device, the second operation on the first result data, based on first co-processor custom instructions.

Systems and methods for processing functions in computational storage

A memory system includes a memory controller having a bank command scheduler implemented in a hardware logic block and a power budget controller including a power budget register and a credit register. The hardware logic block is able to determine a command in a queue to be transmitted to a memory bank over a channel, estimate a power consumption value for the command, and query the power budget controller to determine if the power consumption value is within a threshold. If the power consumption value is within the threshold, the hardware logic block receives a grant response from the power budget controller, adds the power consumption value to the credit register value, transmits the command over the channel, and transmits a signal to the power budget controller indicating that the command has been executed and that the power consumption value should be subtracted from the credit register value.

Credit based command scheduling

Various implementations described herein relate to systems and methods for correcting data from memory systems such as a plurality of non-volatile memory devices of a Solid State Drive (SSD), including but not limited to, receiving frames of the data from the plurality of non-volatile memory devices, allocating the frames among pooled frontline Error Correction Code (ECC) decoders, decoding, by the pooled frontline ECC decoders, the frames to output first decoded frames, and returning the first decoded frames to the read channels.

Pooled frontline ECC decoders in memory systems

In one embodiment, a solid state storage drive comprises a plurality of flash memory devices communicatively coupled to a bus and a channel controller communicatively coupled to the bus, the channel controller comprising an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate presently assigned for communications over the bus, and a channel execution unit configured to determine when to place a second command in a command execution queue based at least in part on the aggregate execution time duration. In one embodiment, the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate and a data payload quantity associated with at least one command in the sequence of commands.

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San Jose, CA, United States of America

Jonghyeon Kim