Samsung Electronics Co., Ltd.

Lg Electronics Inc.

Yonsei University

Jonghoon Shin

Yong Ki Lee

Sun-Soo Shin

Kyoungmoon Ahn

Ji-su Kang

Jinsu Hyun

Jaechul Park

Hong-mook Choi

Hyosun Hwang

Seongil Hahm

Jaehyeok Kim

Heonsoo Lee

Taejun Kwon

Jisu Kang

Mijung Noh

Kee Moon Chun

Taehoon Jang

Kiseok Bae

Youngjin Chung

Hyesoo Lee

Kitak Kim

Ingoo Heo

Hyunil Kim

Kyoung Moon Ahn

Hongmook Choi

Kyoungwoo Lee

KyoungMoon Ahn

Ji-Su Kang

Woongsun Kim

Gisoo Seo

Hyunchoong Kim

Hyojoon Jin

A device includes a random number generator configured to generate a random number, a memory configured to store at least one lookup table, and a processing circuit configured to generate a generator based on the random number, create the at least one lookup table based on the generator, and write the created at least one lookup table to the memory, wherein the processing circuit is configured to access the memory based on a first input and a second input, and generate a result of a modular multiplication of the first input by the second input based on the at least one lookup table.

Apparatus and method for modular multiplication resistant to side-channel attack

A security circuit includes a decoder configured to receive input data and output a decoding signal in response to the input data, a first encoder configured to output one of first phenotypes corresponding to any one among integers in N-decimal (N is a natural number of 1 or more) as a first encoding value in response to the decoding signal, a second encoder configured to output one of second phenotypes corresponding to any one among integers in N-decimal as a second encoding value in response to the decoding signal, and a gate module circuit configured to generate output data by performing a logic operation on the first encoding value and the second encoding value.

Security circuit including dual encoder and endecryptor including the security circuit

An authentication apparatus, included in a device supporting a network communication, includes a certificate handler that receives a certificate of an opponent and parses or verifies the certificate of the opponent. Cryptographic primitives receive an authentication request of the opponent, generate a random number in response to the authentication request, generate a challenge corresponding to the random number, and verify a response of the opponent corresponding to the challenge. A shared memory stores the parsed certificate, the random number, the challenge, and the response. An authentication controller controls the certificate handler, the cryptographic primitives, and the shared memory through a register setting, according to an authentication protocol.

Authentication apparatus based on public key cryptosystem, mobile device having the same and authentication method

An electronic device and a method for identifying a location by the electronic device are provided. The electronic device includes a display, a processor electrically connected with the display and a memory, and the memory storing instructions executed by the processor. The processor is configured to obtain a plurality of locations in a space-of-interest, detect a wireless signal from at least one external electronic device located in the space-of-interest or an adjacent area, obtain detection frequency data according to a frequency of detection of the wireless signal, and identify a current location of the electronic device based on at least part of the obtained detection frequency data.

Electronic device and method for identifying location by electronic device

A path for transmitting encrypted data is completely separated from a path for transmitting unencrypted data. To this end, a virtual secure memory is created on an address space. If a central processing unit (CPU) writes data in the virtual secure memory, hardware stores the data in a specific area of a dynamic random access memory (DRAM) after automatically encrypting the data. In the case where the CPU intents to read data, the hardware sends the data to the CPU after automatically decrypting the data read from a specific area of the DRAM.

Computing system having an on-the-fly encryptor and an operating method thereof

A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.

Modular multiplier and modular multiplication method thereof

A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.

Montgomery multiplication method for performing final modular reduction without comparison operation and montgomery multiplier

A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.

Device having secure JTAG and debugging method for the same

This specification relates to an enhancement-type semiconductor device having a passivation layer formed using a photoelectrochemical (PEC) method, and a fabricating method thereof. To this end, a semiconductor device according to one exemplary embodiment includes a GaN layer, an AlGaN layer formed on the GaN layer, a p-GaN layer formed on the AlGaN layer, a gate electrode formed on the p-GaN layer, a source electrode and a drain electrode formed on a partial region of the AlGaN layer, and a passivation layer formed on a partial region of the AlGaN layer, the passivation layer formed between the source electrode and the gate electrode or between the gate electrode and the drain electrode, wherein the passivation layer is formed in a manner of oxidizing a part of the p-GaN layer.

Nitride semiconductor device and fabricating method thereof

A multiplication method and a modular multiplier are provided. The multiplication method includes transforming a redundant-form multiplier by adding a recoding constant to the multiplier, performing recoding by using the transformed multiplier, and performing partial multiplication between the multiplier and a multiplicand using result values of the recoding.

Multiplication method and modular multiplier using redundant form recoding

A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.

Modular arithmatic unit and secure system including the same

Growing community of inventors

Hwaseong-si, South Korea

Jonghoon Shin