Samsung Electronics Co., Ltd.

Jongho Lim

Hyongsik Won

Soonwon Jeong

Yeonjun Sung

Joonwoo Jeon

Jonghyun Park

Sunyoung Kim

Bora Lee

Hoosung Cho

Hongsoo Kim

Sangbok Yun

Kyungjae Park

Hosik Jun

Hanna Heo

Myoungsu Chae

Leeeun Ku

Jaehyuk Lim

Yuna Lee

Hyojeong Kang

Yonggi Cho

A light-emitting diode (LED) package includes a substrate including an insulating material; upper pads on an upper surface of the substrate; a side surface molding layer covering the upper surface of the substrate and side surfaces of the upper pads; an LED chip on the upper surface of the substrate and electrically connected to the upper pads; a fluorescent layer on the LED chip; and a reflection molding layer on the substrate and covering the LED chip, the reflection molding layer including white silicon, wherein the reflection molding layer exposes a portion of side surfaces of the fluorescent layer.

Light emitting diode (LED) package having reflection molding layer covering led chip

A light-emitting diode (LED) package includes a package substrate, an LED chip disposed on a first surface of the package substrate, and a first external connection pad and a second external connection pad disposed on a second surface of the package substrate opposite the first surface. The first external connection pad includes a first side, a second side, a third side and a fourth side, the first side being parallel to the second side, and the third side being parallel to the fourth side. The first side is spaced farther from a center of the package substrate than the second side. A length of the first side is shorter than a length of the second side.

Light emitting diode (LED) package and illuminating device including the same

A light emitting device package includes a first molding member surrounding a heat dissipation frame, a first electrode frame, and a second electrode frame; a first semiconductor light emitting device on the heat dissipation frame and having first and second pads; a second semiconductor light emitting device on the heat dissipation frame and having first and second pads; a wavelength conversion layer on the first and second semiconductor light emitting structures; a first bonding wire connected to the first pad of the first semiconductor light emitting device and the first electrode frame; a second bonding wire connected to the second pad of the second semiconductor light emitting device and the second electrode frame; and an inter-chip bonding wire connecting the second pad of the first semiconductor light emitting device to the first pad of the second semiconductor light emitting device.

Light emitting device package

A vertical type non-volatile memory device includes a substrate having a cell array area of a block unit and an extension area, a vertical contact disposed in the extension area, a plurality of vertical channel structures provided on the substrate in the cell array area, a plurality of dummy channel structures provided on the substrate in the extension area, and a plurality of gate electrode layers and a plurality of interlayer insulation layers stacked alternately on the substrate. In an electrode pad connected to the vertical contact, dummy channel structures are disposed at both sides of the vertical contact and a horizontal cross-sectional surface of each of the plurality of dummy channel structures has a shape which is longer in one direction.

Vertical type non-volatile memory device and method of manufacturing the same

A vertical memory device includes circuit patterns of peripheral circuits on a substrate, the circuit patterns including a lower conductive pattern, cell stack structures over the circuit patterns and spaced apart in a first horizontal direction, wherein each of the cell stack structures includes gate electrodes spaced apart in a vertical direction, a first insulating interlayer covering the cell stack structures and a portion between the cell stack structures, a through via contact passing through the first insulating interlayer between the cell stack structures to contact an upper surface of the lower conductive pattern, at least one dummy through via contact passing through the first insulating interlayer between the cell stack structures and disposed adjacent to the through via contact, and upper wiring on the through via contact.

Vertical memory devices

Growing community of inventors

Yongin-si, South Korea

Jongho Lim