Xilinx, Inc.

Jongheon Jeong

James Karp

Shahin Toutounchi

Michael G Ahrens

Daniel Gitlin

Michael J Hart

Martin L Voogel

Kameswara K Rao

Kevin T Look

Radko Gerard Bankras

Jan Lodewijk De Jong

Matthew H Klein

Amitava Majumdar

Robert W Wells

Richard William Swanson

Glenn O'Rourke

Asim A Bajwa

Jae Cho

Michael M Matera

Anna W Wong

Suraj Ethirajan

In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.

Testing for shorts between internal nodes of a power distribution grid

In the disclosed methods, integrated circuit (IC) dice are manufactured from a common specification, and the IC dice are tested for defective circuitry. Respective defect sets are generated to indicate defective circuitry in the IC die. The dice are assigned to bins based on the respective defect sets. For each bin, all IC dice assigned to the bin have equivalent respective defect sets. Product definitions are provided, and each product definition indicates a respective set of circuitry required for a corresponding product. Respective sets of packages are manufactured for each product. In the manufacturing of each package of a respective set of packages for each product, one or more IC dice are selected from a subset of the plurality of bins such that the IC dice have respective defect sets allowed by the product definition of the product. The selected IC dice are then manufactured into the package.

Methods of making integrated circuit products

Method and apparatus for self-regulated burn-in of an integrated circuit (IC) is described. One embodiment of a method of burn-in for the IC includes: configuring programmable resources of the IC device based on a burn-in pattern to implement a load controller, the load controller having a plurality of heat core circuits. The load controller is initialized with a number of enabled heat core circuits of the plurality of heat core circuits. A junction temperature is measured in the IC device after a measurement period has elapsed. The junction temperature is compared with a set-point temperature. The number of the enabled heat core circuits is increased if the junction temperature is less than the set-point temperature, or the number of the enabled heat core circuits is decreased if the junction temperature is greater than the set-point temperature.

Method and apparatus for self-regulated burn-in of an integrated circuit

A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Three-terminal non-volatile memory element with hybrid gate dielectric

An MOS transistor is programmed in a non-volatile memory cell. A storage capacitor in the non-volatile memory cell is used to enhance programming efficiency by providing additional charge to the programming terminal of the MOS transistor during breakdown of the gate dielectric, thus avoiding soft programming faults. In a particular embodiment the storage capacitor is a second MOS transistor having a thicker gate dielectric layer than the dielectric layer of the programmable MOS transistor.

Non-volatile memory cell with charge storage element and method of programming

A PMOS transistor is programmed as a non-volatile memory element by operating the PMOS transistor in accumulation mode. This facilitates merging the source and drain regions to form a low-resistance path because most heating occurs on the channel side of the gate dielectric, rather than on the gate terminal side. In a particular embodiment, boron is used as the dopant. Boron has a higher diffusivity than arsenic or phosphorous, which are typical n-type dopants. Boron's higher diffusivity promotes merging the source and drain regions.

PMOS three-terminal non-volatile memory element and method of programming

A storage transistor is programmed as a non-volatile memory element by biasing the source and drain while a programming voltage is applied to the gate. The substrate is held at a different potential than the source/drain to insure that the greatest difference in voltage during the programming step occurs between the channel region and the gate, rather than the gate and the source/drain. The programming voltage heats the channel region to form a non-volatile low-resistance connection between the source and drain, which is read to determine the programmed state.

Method of programming a three-terminal non-volatile memory element using source-drain bias

A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Ballast resistor with reduced area for ESD protection

Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Non-volatile memory array using gate breakdown structures

Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located &ldquo;on chip&rdquo; with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

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Palo Alto, CA, United States of America

Jongheon Jeong