Samsung Display Co., Ltd.

Samsung Displayco., Ltd.

Jonghee Kim

Jaekeun Lim

Chongchul Chai

Youngwan Seo

Boyong Chung

Bogyeong Kim

Ji-Sun Kim

Byungseok Choi

Tak-young Lee

BoYong Chung

Kyoungju Shin

Junhyun Park

Sang-uk Lim

Hyuk Hwan Kim

Takyoung Lee

Chang-Soo Lee

Sunghwan Kim

Joosun Yoon

Kyoungseok Son

Cholho Kim

Jisun Kim

Doo-young Lee

Se-hyang Kim

Sanguk Lim

Dooyoung Lee

Chang-soo Lee

Doo-Young Lee

A display device includes a display panel and a gate driver. The gate driver includes an N-th stage (where N is a natural number) configured to output an N-th scan gate signal and output an N-th sensing gate signal. The N-th stage includes a compensator, a sixth transistor including a control electrode connected to a first node, and a ninth transistor including a control electrode connected to the first node. In a variable frequency mode, the compensator outputs a second signal to the first node in response to a first signal, and the sixth transistor does not output the N-th scan gate signal when the ninth transistor outputs the N-th sensing gate signal based on the sensing clock signal, the voltage of the first node, and the voltage of the second node.

Display device

A display device includes a display panel including pixels, a gate driver applying gate signals to the pixels, a data driver applying data voltages to the pixels, sensing selected pixels among the pixels, and applying the data voltages to the selected pixels after the selected pixels are sensed in one frame, and a timing controller controlling the gate driver and the data driver.

Display device and method of driving the same

A display device includes a display panel including a plurality of pixels respectively connected to a plurality of data lines and a plurality of scan lines, a data driver which outputs data signals to the plurality of data lines including a first data line and a second data line branched from a data output terminal connected to the data driver, and a scan driver which outputs scan signals to the plurality of scan lines. A first scan output terminal and a second scan output terminal respectively connected to the plurality of scan lines are connected to the scan driver. One of the first scan output terminal and the second scan output terminal is connected to a resistance.

Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

Gate driving circuit and display apparatus including the same

A gate driver includes stages. Each stage includes: a first output part for outputting a carry signal in response to a voltage of a first node; a first input part for controlling the voltage of the first node in response to a previous carry signal; a second input part for controlling the voltage of the first node in response to a first next carry signal; a second output part for outputting a scan signal in response to the voltage of the first node; a third output part for outputting a sensing signal in response to the voltage of the first node; and a scan signal control part for applying a first low power voltage to an output terminal of the second output part to which the scan signal is output in response to a second next carry signal of which a pulse is generated before the first next carry signal.

Gate driver and display device having the same

A display device includes a display panel including a plurality of pixels, a gate driver which provides a gate signal to corresponding pixels of the plurality of pixels, a data driver which provides a data voltage to the corresponding pixels of the plurality of pixels, a power voltage generator which provides a pixel power voltage to each of the plurality of pixels, and provides a gate power voltage to the gate driver, and a controller which provides a gate control signal to the gate driver. The pixel power voltage, the data voltage, and the gate control signal sequentially have a ground voltage level in response to a power-off signal.

A scan driver includes stages, and first to third clock signals are applied to the stages, respectively. A falling time of the first clock signal is shorter than falling times of the second and third clock signals.

Scan driver and display apparatus comprising the same

A scan driver includes a plurality of stages, each of the plurality of stages including: a first controller to control voltage levels of a first control node and a second control node in response to a first start signal and a second start signal, and to output a first carry signal; a second controller to control voltage levels of a third control node and a fourth control node in response to the first start signal and the second start signal, and to output a second carry signal; and an output circuit including: a pull-up transistor having a gate connected to the first control node; and a pull-down transistor having a gate connected to the third control node. The output circuit is to output a scan signal based on an on voltage output through the pull-up transistor and an off voltage output through the pull-down transistor.

Scan driver and display device including the same

A pixel circuit including an organic light emitting diode, a first transistor configured to drive the organic light emitting diode, a second transistor electrically connected between a gate node of the first transistor and a data line, a third transistor electrically connected between a source node of the first transistor and an initialization voltage line and a storage capacitor electrically connected between the gate node and the source node of the first transistor. In a data writing period in which the storage capacitor is charged with electric charges, a turn-off time of the third transistor lags compared to a turn-off time of the second transistor.

Pixel circuit, display device including the same, and method of driving pixel circuit

The display device includes: a display panel including a plurality of gate lines extending in a first direction and arranged in a second direction, a plurality of data lines extending in the second direction and arranged in the first direction, and a plurality of dots arranged in the first and second directions; a gate driver configured to sequentially supply a gate signal to the plurality of gate lines; and a data driver configured to supply a plurality of data signals to the plurality of data lines, respectively. The gate driver includes sub-gate drivers. The sub-gate drivers are disposed in the first direction to supply the gate signal to at least two positions of each gate line. Each of the sub-gate drivers includes a plurality of stages and each stage is disposed in at least one dot.

Display device with a reduced size of a bezel area

A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.

Gate driving circuit

A display device including: a display panel including a gate line and a data line; and a shift register including a stage for driving the gate line. The stage may include a first driving unit in a display area of the display panel and a second driving unit in a non-display area of the display panel.

Provided is a display device. The display device includes a display panel, a gate driving circuit, a sensor part, and a control voltage generator. The gate driving circuit includes driving transistors including a first control electrode and a second control electrode. The sensor part is configured to measure an environmental factor that changes a threshold voltage of the driving transistors. The control voltage generator is configured to apply to the second control electrode a control voltage for controlling the threshold voltage of the driving transistors on the basis of the environmental factor measured by the sensor part.

Gate driving circuit and display device including the same

A gate driving circuit includes a plurality of stages to provide gate signals to gate lines of a display panel. At least one of the stages includes an input circuit receiving a carry signal from a previous stage. A first output circuit outputs a first clock signal as a gate signal. The second output circuit outputs the clock signal as a carry signal. The discharge hold circuit delivers the clock signal to a node based on the clock signal and discharges the node as a second voltage based on the carry signal. The pull down circuit discharges the gate signal as a first voltage based on a signal of the node and a succeeding carry signal from a succeeding stage and discharges another node and the carry signal as the second voltage. The switching circuit delivers the carry signal from the previous stage based on a second clock signal.

Gate driving circuit having high reliability and display device including the same

A gate driving circuit includes a first driving stage driving a first gate line included in a display panel. The first driving stage includes a first output transistor outputting a first carry signal on the basis of a first clock signal in response to a voltage of a first node, a second output transistor outputting a first gate signal on the basis of the first clock signal in response to the voltage of the first node, a first control transistor applying a second clock signal to a second node, a second control transistor applying a start signal to the first node in response to a voltage of the second node, and a third control transistor applying a first discharge voltage to the first node in response to the first carry signal.

Growing community of inventors

Yongin-si, South Korea

Jonghee Kim