Qualcomm Incorporated

International Business Machines Corporation

Qualcomm Mems Technologies, Inc.

Snaptrack Incorporated

Jonghae Kim

Changhan Hobie Yun

Mario Francisco Velez

Chengjie Zuo

Daeik Daniel Kim

Je-Hsiung Lan

David Francis Berdy

Matthew Michael Nowak

Niranjan Sunil Mudakatte

Robert Paul Mikulka

Chi Shun Lo

Periannan Chidambaram

Moon Jung Kim

Ranadeep Dutta

Shiqun Gu

Milind Shah

Choongyeun Cho

Moon Ju Kim

James Randal Moulic

Jean-Olivier Plouchart

Robert E Trzcinski

Stanley Seungchul Song

Ravindra Vaman Shenoy

Kai Liu

Sang-June Park

Feng Wang

Dae Ik Kim

Xiangdong Zhang

Brian Matthew Henderson

Jean-Oliver Plouchart

Young Kyu Song

Xiaonan Zhang

Thomas R Toms

Yunfei Ma

Xiaoju Yu

Evgeni Petrovich Gousev

Aniket Patil

Ryan David Lane

Bharani Chava

Abinash Roy

Xia Li

Hong Bok We

John Hyunchul Hong

Wei-Chuan Chen

Lew G Chua-Eoan

Philip Jason Stephanou

Puay Hoe See

Kwan-Yu Lai

Nosun Park

Eric Yee

Anthony K Stamper

Zhong-Xiang He

Douglas Duane Coolbaugh

Jeffrey Bowman Johnson

Francesco Carobolante

Ebenezer E Eshun

Anil Kumar Chinthakindi

Beomsup Kim

Seyfollah Seyfollahi Bazarjani

Jon Lasiter

Giridhar Nallapati

Donald William Kidwell, Jr

Daniel Daeik Kim

Arvind Chandrasekaran

Jin-Su Ko

Sungjae Lee

Manuel Aldrete

Paragkumar Ajaybhai Thadesar

Jie Fu

Scott Keith Springer

Jitae Kim

Rui Tang

Hong Hua Song

Seung Hyuk Kang

Clarence Chui

Kern Rim

Bin Yang

Charles Chengyea Leu

Edgar Schmidhammer

Jungwon Suh

Christian Hoffmann

Aristotele Hadjichristos

Chin-Kwan Kim

Venugopal Boynapalli

Hyeokjin Lim

Pratyush Kamal

Foua Vang

Justin Phelps Black

Jianwen Xu

Deepak Sharma

Richard C Ferri

Thomas Myers

Peijie Feng

Jong-Hoon Lee

Uei-Ming Jow

Stefan Leopold Hatzl

Jihong Choi

William Michael Stone

Francesco Carrara

A package comprising a substrate; a first integrated device coupled to the substrate through at least a first plurality of solder interconnects; a second integrated device coupled to the substrate through at least a second plurality of solder interconnects; a first bridge coupled to the first integrated device and the second integrated device through at least a third plurality of solder interconnects, wherein the first bridge is configured to provide at least one first electrical path between the first integrated device and the second integrated device, and wherein the first bridge is coupled to a top portion of the first integrated device and a top portion of the second integrated device, through at least the third plurality of solder interconnects; and a second bridge coupled to the first integrated device and the second integrated device through a fourth plurality of solder interconnects.

Package comprising integrated devices and bridge coupling top sides of integrated devices

A compact, hybrid, acoustic wave filter structure is disclosed. In an aspect an apparatus comprises a substrate; a first, multi-layer metallization structure disposed above the substrate; a plurality of pillar structures disposed above, and electrically coupled to, the first metallization structure; a second metallization structure disposed above, an electrically coupled to, the plurality of pillar structures. An acoustic unit (AU) is disposed between the first and second metallization structures and adjacent to at least one of the pillar structures. The AU comprises a surface acoustic wave or bulk acoustic wave acoustic resonator that is electrically coupled to a capacitor and an inductor. The capacitor comprises a metal-insulation-metal capacitor that is formed from a portion of the first metallization structure and optionally also from at least one pillar structure and a portion of the second metallization structure. The inductor is comprised of a second portion of the first metallization structure.

Compact hybrid acoustic wave filter structure

A device comprising a die substrate, a plurality of interconnects located over the die substrate, wherein the plurality of interconnects are configured to operate as an inductor, at least one magnetic layer that surrounds at least part of the plurality of interconnects; and at least one dielectric layer that surrounds the at least one magnetic layer.

Integrated device and integrated passive device comprising magnetic material

A substrate that includes an encapsulation layer, a first acoustic resonator, a second acoustic resonator, at least one first dielectric layer, a plurality of first interconnects, at least one second dielectric layer, and a plurality of second interconnects. The first acoustic resonator is located in the encapsulation layer. The first acoustic resonator includes a first piezoelectric substrate comprising a first thickness. The second acoustic is located in the encapsulation layer. The second acoustic resonator includes a second piezoelectric substrate comprising a second thickness that is different than the first thickness. The at least one first dielectric layer is coupled to a first surface of the encapsulation layer. The plurality of first interconnects is coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer.

Substrate comprising acoustic resonators configured as at least one acoustic filter

Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.

Integrated circuit assembly with hybrid bonding

A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

3D inductor design using bundle substrate vias

Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.

Wideband filter with resonators and inductors

Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods. The antenna module includes a RF transceiver whose circuitry is split over multiple semiconductor dies ('dies') so different semiconductor devices can be formed in different semiconductor structures. The antenna module is provided as a 3D build-up on mold package to reduce lengths of die-to-die (D2D) interconnections between circuits in different dies. First and second die packages that include respective first and second dies encapsulated in respective first and second mold layers are coupled to each other in a vertical direction in a 3D stacked arrangement with active faces of the first and second dies facing each other to provide a reduced distance between the active faces of the first and second dies. An antenna is stacked on the second die package to provide an antenna(s) for the antenna module.

Antenna modules employing three-dimensional (3D) build-up on mold package to support efficient integration of radio-frequency (RF) circuitry, and related fabrication methods

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods

In an aspect, an apparatus is disclosed that includes a surface-mounted integrated circuit package housing an active oscillator circuit; an integrated ceramic resonator formed from a ceramic substrate having an upper planar surface receiving the surface-mounted integrated circuit package, the integrated ceramic resonator including a plurality of conductive walls forming a conductive periphery of a ceramic cavity in the ceramic substrate, a conductive rod extending vertically into the ceramic cavity, wherein the conductive rod is isolated from contact with the conductive periphery of the ceramic cavity, a first conductive material extending vertically through the upper planar surface of the ceramic substrate for connecting the conductive periphery of the ceramic cavity to the surface-mounted integrated circuit package housing the active oscillator circuit; and a second conductive material extending through the upper planar surface of the ceramic substrate for connecting the conductive rod to the surface-mounted integrated circuit package.

Radio frequency oscillator with ceramic resonator and surface-mounted integrated circuit package

Disclosed is a radio frequency (RF) filter that vertically integrates an acoustic die with inductors formed in one or more layers above the acoustic die. The acoustic die may be over-molded so that the acoustic dome, important for maintaining acoustic integrity, may be protected.

Backend and acoustic process integration for high-Q filter

An integrated device that includes a die substrate comprising a plurality of transistors, an interconnection portion coupled to the die substrate, and a packaging portion coupled to the interconnection portion. The interconnection portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.

A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.

Hybrid reconstituted substrate for electronic packaging

Disclosed are apparatuses and techniques for fabricating an apparatus including a semiconductor device. The semiconductor device may include: a die, a thermally conductive interface that includes a thermal bridge interposer (THBI) structure, and a substrate. The die is coupled to the substrate by the thermally conductive interface and at least a portion of the die is coupled to the substrate by the THBI structure.

Thermal bridge interposer structure

An integrated circuit (IC) includes a substrate and a thin film resistor (TFR) device structure. The TFR device structure includes a first portion of a first metallization layer and a second portion of the first metallization layer on the substrate. The TFR device structure also includes a first portion of a dielectric layer on the first portion of the first metallization layer and a second portion of the dielectric layer on the second portion of the first metallization layer. The TFR device structure further includes a first portion of a second metallization layer on the first portion of the dielectric layer and a second portion of the second metallization layer on the second portion of the dielectric layer. The TFR device structure also includes a first portion of a third metallization layer coupling the first portion of the second metallization layer to the second portion of the second metallization layer.

Thin film resistor (TFR) device structure for high performance radio frequency (RF) filter design

Growing community of inventors

San Diego, CA, United States of America

Jonghae Kim