Samsung Electronics Co., Ltd.

Shinshu University

Jongchul Park

Jong-Kyu Kim

Inho Kim

Hyungjoon Kwon

Sang-Kuk Kim

Jongsoon Park

Jeongyun Lee

Gwang-Hyun Baek

Sanghyun Lee

Byoungjae Bae

Yil-hyung Lee

Woohyun Lee

Sangmin Lee

Jaehun Seo

Youngmook Oh

Jung-Ik Oh

Sungwoo Kang

Sangsup Jeong

Sechung Oh

Eunsun Noh

Myungsun Kim

Sangbok Han

Shin Kwon

Byoung-Suhk Kim

Ick-Soo Kim

Kazuchika Ohta

Hyun-woo Yang

Wonjun Lee

Insun Park

Shin-Jae Kang

Byung-Jin Kang

Vladimir Urazaev

Oik Kwon

Ken Tokashiki

Jinhye Bae

Haegeon Jung

Kwonsik Kim

Ji-Young Min

Hyojeong Lee

Kyung Rae Byun

Heedon Hwang

Insang Jeon

Kwangwon Ko

Seyoun Lim

Hyunggoo Lee

Woogwan Shim

Bokyoung Lee

Hyeji Yoon

Yeondo Jung

Sungyoon Chung

Jinyoung Kim

Woojin Kim

Cheol Jin Kim

Jinwook Lee

Chanjin Park

Hyuk Kim

Joon-Soo Park

Young-Ju Park

Keunhee Bai

Hak-Sun Lee

Hongsik Shin

Soonoh Park

Joonkyu Rhee

Wonhyuk Lee

Kukhan Yoon

Young-Seok Choi

Cheolhong Kim

Jinkyu Koo

Yeonji Kim

Han-Na Cho

Kyungrae Byun

Dong Kwon Kim

Hyunsoo Shin

HyunHo Jung

Minyoung Kang

Ki-jin Park

Seokwoo Nam

Kwangyoung Oh

Seungju Park

Seungjun Kim

Hyonwook Ra

Hyobin Lee

Jaesuk Kwon

Seonguk Seo

Changwoo Sun

A semiconductor device includes a substrate including a first active pattern and a second active pattern, a gate electrode including a first gate electrode on the first active pattern and a second gate electrode on the second active pattern, a gate cutting pattern between the first and second gate electrodes, gate spacers on opposing side surfaces of the gate electrode, and a gate capping pattern on top surfaces of the gate electrode, the gate cutting pattern, and the gate spacers and extending in the first direction. The gate cutting pattern includes a first and second side surfaces, which are opposite to each other in a second direction crossing the first direction. The first and side surfaces are in contact with respective ones of the gate spacers, and the top surface of the gate cutting pattern is closer to the substrate than the top surfaces of the pair of gate spacers.

Semiconductor device and method of fabricating the same

A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.

Semiconductor device including self-aligned contact and method of manufacturing the semiconductor device

A plasma etching apparatus includes a chuck configured to support a wafer, and a voltage application unit. The voltage application unit includes a first voltage application part configured to apply a first voltage to the wafer on the chuck, and a second voltage application part configured to apply a second voltage to the wafer on the chuck, the second voltage being different from the first voltage.

Plasma etching apparatus, plasma etching method using the same, and semiconductor fabrication method using the same

A semiconductor device including a gate pattern on a substrate and including a gate dielectric layer, a gate electrode, and a gate capping pattern that are sequentially stacked; a gate spacer on a sidewall of the gate pattern; a source/drain pattern in the substrate; a contact pad on the source/drain pattern, a source/drain contact on the contact pad; and a buried dielectric pattern between the gate spacer and the source/drain contact, wherein the gate spacer includes a first segment between the gate electrode and the source/drain pattern; a second segment that extends from the first segment and between the gate electrode and the source/drain contact; and a third segment on the second segment, the buried dielectric pattern is between the third segment and the source/drain contact, and is absent between the first segment and the contact pad and is absent between the second segment and the source/drain contact.

A semiconductor device includes a device isolation layer on a substrate; pattern groups including fin patterns extending in a first direction; and gate structures extending in a second direction to intersect the fin patterns. A first pattern group, among the pattern groups, may include first fin patterns. At least a portion of the first fin patterns may be arranged with a first pitch in the second direction. The first pattern group may include a first planar portion extending from a first recess portion. A central axis of the first recess portion may be spaced apart from a central axis of one of the first fin patterns by a first distance in the second direction. The first planar portion may have a first width in the second direction and being greater than the first pitch. The first distance may be about 0.8 times to about 1.2 times the first pitch.

Semiconductor devices and method of manufacturing the same

A semiconductor device includes a substrate having first and second active regions. A first active pattern is on the first active region and includes first source/drain patterns and a first channel pattern therebetween. A second active pattern is on the second active region and includes second source/drain patterns and a second channel pattern therebetween. A gate electrode includes a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern. A gate cutting pattern is between the first and second gate electrodes and separates the first and second gate electrodes from each other. A pair of gate spacers is on opposite sidewalls of the first gate electrode extending along opposite sidewalls of the gate cutting pattern towards the second gate electrode. The gate cutting pattern includes first to third parts having maximum widths that increase from the first to the third part.

Semiconductor device

A wafer processing apparatus is provided. The wafer processing apparatus includes a chamber body defining a plasma region configured that plasma is generated in the plasma region, a wafer support arranged in the chamber body and configured to support a wafer, first and second electrodes arranged between the wafer support and the plasma region and having apertures configured to guide a path of ions of the plasma, a first power source configured to apply, to the first electrode, a voltage that is higher than a voltage applied to the second electrode, and a second power source configured to apply, to the wafer support, a voltage that is higher than the voltage applied to the second electrode.

Wafer processing apparatus

Disclosed are a training method of an artificial intelligence (AI) model configured to provide information identifying a recommendation item and a recommended user, and an electronic apparatus for training an AI model. The training method includes obtaining user data and item data; generating a first semantic vector at a first time interval based on the user data; generating a second semantic vector at the first time interval based on the item data; generating a vector that represents a relevance between the first semantic vector and the second semantic vector at the first time interval; storing data corresponding to the generated vector, the first semantic vector, and the second semantic vector; and obtaining an updated weight for the first AI model by training the first AI model based on the stored data.

Learning method of AI model and electronic apparatus

An integrated circuit device includes a fin-type active area that extends on a substrate in a first direction, a gate structure that extends on the substrate in a second direction and crosses the fin-type active area, source/drain areas arranged on first and second sides of the gate structure, and a contact structure electrically connected to the source/drain areas. The source/drain areas comprise a plurality of merged source/drain structures. Each source/drain area comprises a plurality of first points respectively located on an upper surface of the source/drain area at a center of each source/drain structure, and each source/drain area comprises at least one second point respectively located on the upper surface of the source/drain area where side surfaces of adjacent source/drain structures merge with one another. A bottom surface of the contact structure is non-uniform and corresponds to the first and second points.

Integrated circuit devices and methods of manufacturing the same

A method of manufacturing a data storage device may include forming a magnetic tunnel junction layer on a substrate, irradiating a first ion beam on the magnetic tunnel junction layer to form magnetic tunnel junction patterns separated from each other, irradiating a second ion beam on the magnetic tunnel junction layer, and irradiating a third ion beam on the magnetic tunnel junction layer. The first ion beam may be irradiated at a first incident angle. The second ion beam may be irradiated at a second incident angle that may be smaller than the first incident angle. The third ion beam may be irradiated to form sidewall insulating patterns on sidewalls of the magnetic tunnel junction patterns based on re-depositing materials separated by the third ion beam on the sidewalls of the magnetic tunnel junction patterns.

Data storage devices and methods for manufacturing the same

A 5generation (5G) or 6generation (6G) communication system for supporting higher data rates, compared to that of a 4generation (4G) communication system such as a long term evolution (LTE) communication system are provided. An apparatus and a method for load balancing in a wireless communication system are provided. The apparatus includes a transceiver, a memory storing one or more instructions, and at least one processor configured to execute the one or more instructions stored in the memory to receive first information about a relation between a base station (BS) and a user equipment (UE) from each of a plurality of BSs, determine, based on the first information, a number of UEs on which handover has to be performed from among UEs served by each of the plurality of BSs, and transmit, to each of the plurality of BSs, priority information determined based on the number of UEs.

Apparatus and method for load balancing in wireless communication system

Growing community of inventors

Seongnam-si, South Korea

Jongchul Park