Samsung Electronics Co., Ltd.

Jongchan Shin

Changmin Park

Jinwoo Jeong

Jaeseok Yang

Moon Gi Cho

Hyeonuk Kim

Eryung Hwang

Wandon Kim

Rakhwan Kim

Eui Bok Lee

Noyoung Chung

Hyunbae Lee

Seungseok Ha

Ki Chul Park

Sunyoung Noh

Minjoo Lee

Woojeong Shin

Seowoo Nam

A semiconductor device includes a logic cell on a substrate and a first metal layer on the logic cell. The first metal layer includes first and second power lines that extend in a first direction, and first, second, and third lower interconnection lines, which are respectively disposed on first, second, and third interconnection tracks defined between the first and second power lines that extend in the first direction parallel to each other. The first lower interconnection line includes first and second interconnection lines spaced apart from each other by a first distance, and the third lower interconnection line includes third and fourth interconnection lines spaced apart from each other by a second distance. The first and third interconnection lines have first and second ends, respectively, which face the second and fourth interconnection lines, respectively, and have different curvatures.

Semiconductor devices and methods of fabricating the same

Disclosed is a semiconductor device including a substrate, a first interlayer dielectric layer on the substrate, a plurality of first vias in the first interlayer dielectric layer, a second interlayer dielectric layer on the first interlayer dielectric layer, and a first power line and a first lower line in the second interlayer dielectric layer that are electrically connected to respective ones of the first vias. A first width in a first direction of the first power line is greater than a second width in the first direction of the first lower line. The first power line includes a first metallic material. The first lower line includes a second metallic material. The first vias includes a third metallic material. The first, second, and third metallic materials are different from each other.

Semiconductor device

A semiconductor device includes; a substrate including a first region and a second region adjacent to the first region in a first direction, a pair of active patterns adjacently disposed on the substrate, wherein the pair of active patterns includes a first active pattern extending in the first direction and a second active pattern extending in parallel with the first active pattern, a first gate electrode on the first region and extending in a second direction that intersect the first direction across the first active pattern and the second active pattern, and a second gate electrode on the second region and extending in the second direction across the first active pattern and the second active pattern. A width of the first active pattern is greater on the first region than on the second region, a width of the second active pattern is greater on the first region than on the second region, and an interval between the first active pattern and the second active pattern is constant from the first region to the second region.

Semiconductor device and method of fabricating same

Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.

Semiconductor devices having multi-level metallization structures

Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises sequentially forming a target layer and a first mask layer on a substrate, patterning the first mask layer to form a first opening in the first mask layer, forming a spacer covering an inner wall of the first opening, forming on the first mask layer a first photoresist pattern having a second opening vertically overlapping at least a portion of the spacer, forming a third opening in the first mask layer that is adjacent to the first opening by using the spacer as a mask to remove a portion of the first mask layer that is exposed to the second opening, and using the first mask layer and the spacer as a mask to pattern the target layer.

Semiconductor device and method of manufacturing the same

Semiconductor devices

Growing community of inventors

Seongnam-si, South Korea

Jongchan Shin