Samsung Electronics Co., Ltd.

Jongbo Shim

Ji Hwang Kim

Jihwang Kim

Choongbin Yim

Kyoungsei Choi

Dongho Kim

Jungwoo Kim

Jangwoo Lee

Chajea Jo

Sang-Uk Han

Jeonghyun Lee

Eunhee Jung

Hyunkyu Kim

Hyoeun Kim

Seunghoon Yeon

Yonghoe Cho

Hwanpil Park

Hwan Pil Park

Jin-Woo Park

Dongwook Kim

Hyunki Kim

Won Il Lee

Sungeun Pyo

Jinwoo Park

Taehwan Kim

Doohwan Lee

Yongkwan Lee

Youngbae Kim

Kilsoo Kim

Jiyong Park

SeokWon Lee

Younghoon Hyun

Yungcheol Kong

Sungkyu Park

Jungsoo Byun

Junggon Choi

JiSun Hong

Byoungwook Jang

Hyunglak Ma

Taeseok Choi

Sungbum Kim

Jeongmin Kang

Provided is a semiconductor package including a support wiring structure, a semiconductor chip on the support wiring structure, a cover wiring structure on the semiconductor chip, and a filling member filling between the support wiring structure and the cover wiring structure, wherein the cover wiring structure includes a cavity which extends from a lower surface of the cover wiring structure into the cover wiring structure and in which an upper portion of the semiconductor chip is positioned, and a first slot and a second slot respectively having a first width and a second width in a first horizontal direction, the first slot and the second slot communicating with the cavity, and respectively extending to a first side surface and a second side surface of the cover wiring structure, which are opposite to each other in a second horizontal direction which is orthogonal to the first horizontal direction of the cover wiring structure.

Semiconductor package having semiconductor chip positioned in cavity of cover wiring structure

A semiconductor package includes a first package substrate having a lower surface and an upper surface respectively including a plurality of first lower surface pads and a plurality of first upper surface pads, a second package substrate having a lower surface and an upper surface respectively including a plurality of second lower surface pads and a plurality of second upper surface pads, wherein the plurality of second upper surface pads comprise all of the upper surface pads at the upper surface of the second package substrate, a semiconductor chip provided between the first package substrate and the second package substrate and attached onto the first package substrate, and a plurality of metal core structures connecting some of the plurality of first upper surface pads to some of the plurality of second lower surface pads and not vertically overlapping any of the plurality of second upper surface pads, each metal core structure having a metal core.

Semiconductor package

A semiconductor device having a package on package (PoP) structure, in which a fine pitch between package substrates is implemented, a total height of a package is reduced, and reliability is enhanced. The semiconductor package includes a first package substrate including a first body layer and a first passivation layer, a first semiconductor chip on the first package substrate, a second package substrate on the first package substrate, the second package substrate including a second body layer and a second passivation layer, a first connection member on the first package substrate outside the first semiconductor chip, and a gap filler filled between the first package substrate and the second package substrate, wherein the first package substrate includes a first trench, the second package substrate includes a second trench, and the first semiconductor chip is disposed between the first trench and the second trench.

Semiconductor device having package on package structure and method of manufacturing the semiconductor device

A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

Semiconductor packages having a dam structure

A semiconductor package structure includes a package substrate; a semiconductor chip on the package substrate and electrically connected to the package substrate; an interposer substrate above the package substrate and the semiconductor chip, wherein the interposer substrate includes a cavity recessed inward from a lower surface thereof, wherein the semiconductor chip is positioned within the cavity, at least from a plan view; and an adhesive layer positioned inside and outside the cavity, wherein the adhesive layer is formed on all of upper and side surfaces of the semiconductor chip, or on the side surfaces of the semiconductor chip.

Semiconductor package structure having interposer substrate, and stacked semiconductor package structure including the same

A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.

Semiconductor package including an interposer and method of fabricating the same

A semiconductor package includes a package substrate, an interposer, a semiconductor chip between the package substrate and the interposer, a plurality of conductive connectors between the package substrate and the interposer, and a capacitor stack structure between the package substrate and the interposer, he capacitor stack structure including a first capacitor connected to the package substrate, and a second capacitor connected to the interposer.

A semiconductor package comprises a package substrate, a semiconductor chip on the package substrate, and an interposer substrate on the semiconductor chip. The interposer substrate comprises a first surface facing the semiconductor chip and a trench in the first surface, the trench vertically overlapping the semiconductor chip. An insulating filler is provided between the semiconductor chip and the interposer substrate, and at least partially fills the trench of the interposer substrate.

Semiconductor package including interposer and method of manufacturing the semiconductor package

A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

Semiconductor package including a support solder ball

Provided is a semiconductor package comprising a lower package that includes a lower substrate and a lower semiconductor chip, an interposer substrate on the lower package and having a plurality of holes that penetrate the interposer substrate, a thermal radiation structure that includes a supporter on a top surface of the interposer substrate and a plurality of protrusions in the holes of the interposer substrate, and a thermal conductive layer between the lower semiconductor chip and the protrusions of the thermal radiation structure.

A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

Semiconductor package substrate and semiconductor package including the same

A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a molding layer covering side walls of the first semiconductor chip and including through holes, an interposer on the first semiconductor chip and the molding layer, conductive connectors in the through holes of the molding layer and connected to the first package substrate and the interposer, and an insulating filler including a first portion that fills the through holes of the molding layer so as to surround side walls of the conductive connectors.

Methods of manufacturing semiconductor packages

A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate, wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.

Semiconductor package and method of fabricating the same

A semiconductor package including a first package substrate, a first semiconductor chip on the first package substrate, a first conductive connector on the first package substrate and laterally spaced apart from the first semiconductor chip, an interposer substrate on the first semiconductor chip and electrically connected to the first package substrate through the first conductive connector, the interposer substrate including a first portion overlapping the first semiconductor chip and a plurality of upper conductive pads in the first portion, a plurality of spacers on a lower surface of the first portion of the interposer substrate and positioned so as not to overlap the plurality of upper conductive pads in a plan view, and an insulating filler between the interposer substrate and the first package substrate may be provided.

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Asan-si, South Korea

Jongbo Shim