Samsung Electronics Co., Ltd.

Jong-Yul Park

Chang-Rae Kim

Min-Chul Chung

Sang-jib Han

Sang-Jib Han

Disclosed is a semiconductor memory device, comprising a plurality of sub-word line drivers arranged at all memory cell array blocks in the direction of bit lines and respectively shared by two memory cell array blocks, a plurality of block sense amplifiers arranged at all memory cell array blocks in the direction of word lines and respectively shared by two memory cell array blocks, a plurality of circuit blocks respectively arranged at conjunction areas where areas accommodating sub-word line drivers and block sense amplifiers are crossed; said conjunction areas comprising one or more LA drivers adapted to drive block sense amplifiers, one or more PXiD circuits adapted to generate driving control signals to control sub-word line drivers, and-one or more BSYD circuits adapted to selectively enables LA drivers in response to transmitted block control signals; and a plurality of block control units adapted to generate upper and lower block control signals by combining column and row block address decoding signals and simultaneously activating two or more BSYD circuits with the block control signals.

Method and apparatus for refreshing semiconductor memory

Refresh-type memory with zero write recovery time and no maximum cycle time

A semiconductor memory device and method for its operation are disclosed. The memory device uses refresh-type memory cells, but operates within the same timing parameters as a SRAM. A refreshing operation and a successful read/write operation can both be performed in a read/write cycle, with zero write recovery time. But if the read/write cycle goes long, multiple refreshing operations can also be performed during the read/write cycle. Thus the device operates with no maximum write cycle time limitation. In the disclosed method, an external write command causes the device to store the write address and data to registers instead of to the memory cell array. When the external write command signals that data is present, zero write recovery time is needed, since the registers require no address setup time. Because the memory cell array is not involved in this transaction, refresh operations can proceed as needed during the external write command, no matter how long the external write takes to complete. At a convenient time after the end of the external write command (e.g., during the next external write command), a short pulsed write operation transfers the data to the memory cell array.

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Yongin, South Korea

Jong-Yul Park