Ulsan National Institute of Science and Technology

Jong Yul Park

Kyung Rok Kim

Sung-Ho Kim

Sung Ho Kim

Yu-Jung Jung

Provided is a method of evaluating a performance of a suspended channel plasma wave device (PWD) to evaluate a terahertz emission possibility of the suspended channel PWD based on physical properties of the suspended channel PWD. The method includes an x-axis setting operation of setting an electron drift velocity to be an x-axis; a y-axis setting operation of setting a plasma wave velocity to be a y-axis; and a device performance determining operation of determining an operation of a device by generating a design window based on a plasma wave generation condition of the suspended channel PWD and a relational expression between the plasma wave velocity and the electron drift velocity.

Performance evaluation method of suspended channel plasma wave transistor

A method for evaluating the performance of a plasma transistor comprises: setting a plasma wave velocity, which is adjusted by a gate overdrive voltage, as a first axis; setting an electronic drift velocity, which is adjusted by a drain-to-source voltage, as a second axis; setting a channel length as a third axis; and checking whether the plasma wave transistor is operated as a terahertz emitter according to a change in the performance parameter value of the plasma wave transistor on the basis of a relational expression among the first axis, the second axis, and the third axis.

Method for evaluating performance of plasma wave transistor

Aspects of the present invention relate to a method for manufacturing a high-performance and low-power field effect transistor (FET) element of which surface roughness scattering is minimized or removed, comprising: a first step of etching a strained silicon substrate into a pin structure; a second step of stacking undoped SiGe thereon; a third step of etching the undoped SiGe; a fourth step of etching after performing lithography; a fifth step of stacking doped SiGe thereon; a sixth step of etching the doped SiGe after performing lithography; and a step of forming a transistor element by sequentially stacking an oxide and a gate metal on the doped SiGe and there is an effect of enabling the implementation of a Fin HEMT capable of having all of good channel controllability and a high on-current, which are advantages of a FinFET, and high electron mobility, which is an advantage of an HEMT.

Growing community of inventors

Seoul, South Korea

Jong Yul Park