Hynix Semiconductor Inc.

Skhynix Inc.

Jong Yeol Yang

Jong Sam Kim

Yin Jae Lee

Sun Mo An

Doo Chan Lee

A fuse circuit may include a plurality of first fuse sets and a plurality of second fuse sets. The plurality of first fuse sets may be used to store a defect address detected before packaging of a semiconductor apparatus. The plurality of second fuse sets may be used to store a defect address detected after the packaging. The plurality of first fuse sets may be shared by a plurality of first redundant word lines, and the plurality of second fuse sets may be in one-to-one correspondence with a plurality of second redundant word lines.

Fuse circuit, repair control circuit, and semiconductor apparatus including the same

A memory device may include a command controller configured to buffer an address based on a refresh enable signal and a repair enable signal. The memory device may include a fuse circuit configured to control a rupture operation of a refresh cell array and repair cell array corresponding to the address according to the refresh enable signal and the repair enable signal, and output a refresh control signal and a repair control signal during a boot-up operation. The memory device may include a refresh controller configured to control a refresh operation of a bank according to a refresh control signal. The memory device may include a repair controller configured to control a repair operation of the bank according to a redundancy signal.

Memory device and system including the same

An embodiment relates to a power control device and a technology capable of stably supplying power when an electrical fuse boots up. The power control device includes a power supply unit, a power driving unit, and an electrical fuse unit. The power supply unit generates a driving signal from a power supply voltage when a control signal is activated. The power driving unit outputs the driving signal when the control signal is activated. The electrical fuse unit generates, when a boot-up enable signal is activated, a clock signal by performing a boot-up operation in response to the driving signal outputted from the power driving unit.

Power control device and method thereof

A semiconductor memory apparatus includes a sense amplifier driving control unit configured to be applied with first and second driving voltages, and generate first to third sense amplifier driving signals in response to a mat enable signal, a sense amplifier enable signal and a power-up signal; a sense amplifier driving unit configured to, in response to the first to third sense amplifier driving signals, connect first and second sense amplifier driving nodes to cause the first and second sense amplifier driving nodes to have substantially the same voltage level, or disconnect the first and second sense amplifier driving nodes to apply first and second sense amplifier driving voltages to the first and second sense amplifier driving nodes; and a sense amplifier configured to be applied with the first and second sense amplifier driving voltages, and sense and amplify a voltage difference of a bit line and a bit line bar.

Semiconductor memory apparatus

A self refresh pulse generation circuit includes a control signal generator configured to generate a control signal asserted for an initial period of a self refresh mode, and a self refresh pulse generator configured to generate a self refresh pulse having a period controlled in response to the control signal, in the self refresh mode.

Self refresh pulse generation circuit

A self-refresh test circuit includes a test clock generation unit, a pulse generation unit, a period signal selection unit, and a self-refresh pulse control unit. The test clock generation unit divides a clock signal to generate a plurality of divided clock signals having different periods when a test enable signal is enabled, and outputs one of the plurality of divided clock signals as a selected clock signal. The pulse generation unit generates a test period signal in response to the selected clock signal. The period signal selection unit outputs one of the test period signal and a self-refresh period signal as a selected period signal. The self-refresh pulse control unit generates a self-refresh pulse in response to a self-refresh exit signal and the selected period signal.

Self-refresh test circuit of semiconductor memory apparatus

A data output circuit in a semiconductor memory apparatus includes a pre-driver configured to receive input data and then produce a pull-up signal and a pull-down signal, a pull-up driver configured to pull-up drive a first node in response to the pull-up signal and provide an additional pull-up drive when a voltage level on the first node transitions, a pull-down driver configured to pull-down drive a second node in response to the pull-down signal and provide an additional pull-down drive when a voltage level on the second node transitions, and a pad coupled to the first and second nodes to generate output data.

Data output circuit in a semiconductor memory apparatus

A refresh control apparatus is provided which is capable of dispersing a peak current at an all-bank refresh mode and reducing the characteristic difference between the banks. The refresh control apparatus includes an internal refresh counter for outputting row address signals to select word lines when a refresh command is inputted from an external circuit, a row decoder for outputting row decoding signals to select all banks in response bank active signals and the row address signals, an enable signal control unit for sequentially outputting at a time interval sense amplifier enable signals in response to the bank active signals and the refresh command, and a sense amplifier for sequentially refreshing all of the banks at a time interval in response to the sense amplifier enable signals.

Apparatus and method for controlling refresh with current dispersion effect in semiconductor device

An auto-refresh control apparatus is provided which includes a counter unit for outputting counter signals in response to an external auto-refresh command signal, and a refresh command signal generating unit for generating internal auto-refresh command signals in response to the counter signals when a test mode signal is activated.

Auto-refresh controlling apparatus

A row active control circuit of a PSRAM controls a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations. The row active signal generating unit generates a row active signal when an active condition is set by the internal active signal. The internal active signal generating unit generates the internal active signal in response to a refresh start signal. The row active control unit generates a row active standby signal with the row active signal in response to the internal active signal. The external active signal generating unit for generating an external active control signal in response to the row active standby signal.

Row active control circuit of pseudo static ranom access memory

A power line control circuit of a semiconductor device in which a width of a power line can be selectively controlled. The power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power line employing the dummy power line. It is therefore possible to easily change the width of the power lines and to reduce the manufacturing cost and the manufacturing time depending on the formation of the power lines. Furthermore, the power line control circuit of the semiconductor device according to the present invention can selectively control the width of the power lines, if appropriate. Accordingly, mesh of optimized power lines can be provided. Furthermore, more stabilized product characteristics can be secured and the yield of semiconductor memory devices can be enhanced. In addition, the power line control circuit of the semiconductor device according to the present invention can selectively change power mesh corresponding to a power line method or operation mode of a product.

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Seoul, South Korea

Jong Yeol Yang