Samsung Electronics Co., Ltd.

Jong-Wook Park

Myung-Gyoo Won

Dong-Hyuk Lee

Sang-Jae Lee

Chang-Ho Lee

Jae-Hoon Kim

Young-Min Lee

Ho-Cheol Lee

Jung-Sik Kim

Yong-Jun Kim

Sung-hee Kim

Chi-Sung Oh

Ye-Sin Ryu

Kyung-Woo Nam

Han-Gu Sohn

Mi-Jo Kim

Yun-Hee Shin

Ki-won Park

Youn-Hyung Kang

Yong-Jun 201-1203 Hyundai Home Town Kim

Young-Mi 201-404 Hyundai 6-Cha I-Park Kang

Hyo-Dae Kim

Eu-Gene Choi

Yu-Seong Jeon

Young-Mi 201-404 Hyundai 6-Cha 1-Park Kang

Hyo-Dae 202-1704 Woncheon Jugong Apt Kim

Jae-Kwon 517-1403 Sinnamusil 5-Danji Apt Kim

A memory device, a memory system, and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells and a write command determination unit (WCDU) that determines whether a write command input to the memory device is (to be) accompanied a masking signal. The WCDU produces a first control signal if the input write command is (to be) accompanied by a masking signal. A data masking unit combines a portion of read data read from the memory cell array with a corresponding portion of input write data corresponding to the write command and generates modulation data in response to the first control signal. An error correction code (ECC) engine generates parity of the modulation data.

Memory device, memory system, and method of operating the same

Memory device, memory system and method of operating the same

A method of operating a semiconductor memory device including a memory cell array and an error correction code (ECC) engine, wherein the memory cell array includes a plurality of memory cells and the ECC engine is configured to perform an error correction operation on data of the memory cell array, may include storing, in a nonvolatile storage, a mapping information indicating physical addresses of normal cells to swap with a portion of fail cells when a first unit of memory cells includes a number of the fail cells exceeding an error correction capability of the ECC engine. The first unit of memory cells of the memory cells may be accessed based on a logical address. The method may include performing a memory operation on the memory cell array selectively based on the mapping information.

Semiconductor memory devices with error correction and methods of operating the same

A semiconductor memory device having a selective error correction code (ECC) function is provided. The semiconductor memory device divides a memory cell array into blocks according to data retention characteristics of memory cells. A block in which there are a plurality of fail cells generated at a refresh rate of a refresh cycle that is longer than a refresh cycle defined by the standards of the semiconductor device is selected from among the divided blocks. The selected block repairs the fail cells by performing the ECC function. The other blocks repair the fail cells by using redundancy cells. Accordingly, a refresh operation is performed on the memory cells of the memory cell array at the refresh rate of the refresh cycle that is longer than the refresh cycle by the standards of the semiconductor device.

Semiconductor memory device having selective ECC function

A semiconductor device and a layout method of a decoupling capacitor thereof are disclosed. The semiconductor device includes a main power/ground voltage voltage supplying line arranged in a first direction; a plurality of decoupling capacitor cells to reduce power noise generated by the power voltage and the ground voltage in the first direction and in a second direction; a plurality of sub power voltage supplying lines arranged in the second direction in a border of the plurality of decoupling capacitor cells; and a plurality of sub ground voltage supplying lines arranged in a net form in the border of the plurality of decoupling capacitor cells, wherein the plurality of decoupling capacitor cells have a first active region arranged to receive the ground voltage and the second active region disposed to receive the power voltage and to avoid a region where an inversion is formed in the decoupling capacitor.

Semiconductor device and layout method of decoupling capacitor thereof

A multi-port memory device includes a refresh register and a refresh controller for preventing refresh starvation in a shared memory unit of the memory device. The memory device further includes a plurality of ports sharing access to the shared memory unit. The refresh register stores information regarding at least one refresh command. The refresh controller determines whether to activate an internal refresh operation at a transition in port authority according to such information stored in the refresh register.

Method, device, and system for preventing refresh starvation in shared memory bank

A multipath accessible semiconductor memory device provides an interface function between processors. The memory device may include a memory cell array having a shared memory area operationally coupled to two or more ports that are independently accessible by two or more processors, an access path forming unit to form a data access path between one of the ports and the shared memory area in response to external signals applied by the processors, and an interface unit having a semaphore area and mailbox areas accessible in the shared memory area by the two or more processors to provide an interface function for communication between the two or more processors.

Multipath accessible semiconductor memory device with host interface between processors

A semiconductor integrated circuit device has a fuse device that can be electrically disconnected without a breakage caused by using a laser beam or current. The semiconductor integrated circuit device employs, as the fuse device for storing status information, a MOSFET of a single polysilicon EEPROM-type cell manufactured through a process of fabricating a volatile semiconductor memory cell array.

Integrated circuit having a non-volatile memory cell transistor as a fuse device

A temperature sensing circuit has numerous trip points in conformity with a temperature change without adding decrease resistance branches, so as to obtain a fine control based on the temperature change. Accordingly, when employed in a semiconductor memory device, the temperature sensing circuit substantially reduces the consumption of refresh electrical power in a stand-by state without decreasing the reliability of the semiconductor memory device.

Temperature sensing circuit for use in semiconductor integrated circuit

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Suwon-si, South Korea

Jong-Wook Park