Samsung Electronics Co., Ltd.

Daewoong Pharmaceutical Co., Ltd.

Ahn-gook Pharmaceutical Co., Ltd.

Jong-Wook Lee

Yong-Hoon Son

Yu-Gyun Shin

Jong-Hyuk Kang

Si-Young Choi

Pil-Kyu Kang

Young-Eun Lee

Byeong-Chan Lee

Deok-Hyung Lee

In-Soo Jung

Young-pil Kim

Sun-Ghil Lee

Min-Gu Kang

Sung-Kwan Kang

Jung-ho Kim

Dae-lok Bae

Deok-hyung Lee

Seung-woo Choi

Sung-Min Kim

Sang-Ho Lee

Jun-ho Lee

Jin-bum Kim

Chang-Kyun Han

Jin Auh

Young-June Shin

Taek-Joo Lim

Eun-Ji Koh

Hyo-Jin Moon

Choong-Ho Lee

Myeong-Cheol Kim

Dong-Won Kim

Cheol Kyu Kim

Chang-Hwan Kim

Kyoung-hwan Yeo

Jong-Seo Hong

Jong-Chan Shin

Yong-Won Cha

Hion-suck Baik

Kang-Jin Lee

Sung-Hum Yeon

Soo-Im Chang

Il-Sup Kim

Dong-Oh Han

Tae-Hoo Yi

In-Deog Bae

Seung-In Choe

Ji-Hye Lee

Jun-Seok Lee

Ho-Young Kwak

Kang-Hyun Leem

InSoo Jung

Seong-ghil Lee

Il-gon Kim

Seo-jae Lee

In a vertical-type memory device and a method of manufacturing the vertical-type memory device, the vertical memory device includes an insulation layer pattern of a linear shape provided on a substrate, pillar-shaped single-crystalline semiconductor patterns provided on both sidewalls of the insulation layer pattern and transistors provided on a sidewall of each of the single-crystalline semiconductor patterns. The transistors are arranged in a vertical direction of the single-crystalline semiconductor pattern, and thus the memory device may be highly integrated.

Vertical-type semiconductor devices and methods of manufacturing the same

Provided is a pharmaceutical composition for preventing or treating hyperlipidemia comprising (4S,5R)-5-[3,5-bis(trifluoromethyl)phenyl]-3-({2-[4-fluoro-2-methoxy-5-(propan-2-yl)phenyl]-5-(trifluoromethyl)phenyl}methyl)-4-methyl-1,3-oxazolidin-2-one or its pharmaceutically acceptable salt; and an angiotensin II receptor blocker as active ingredients.

Pharmaceutical composition for preventing or treating hyperlipidemia

The present invention is a method for treating hyperlipidemia comprising (4S,5R)-5-[3,5-bis(trifluoromethyl)phenyl]-3-({2-[4-fluoro-2-methoxy-5-(propan-2-yl)phenyl]-5-(trifluoromethyl)phenyl}methyl)-4-methyl-1,3-oxazolidin-2-one or its pharmaceutically acceptable salt and amlodipine or its pharmaceutically acceptable salt at a synergistic ratio of about 4:1.

Pharmaceutical composition for preventing or treating hypertriglyceridemia or hypertriglyceridemia-associated diseases

In a vertical-type semiconductor device, a method of manufacturing the same and a method of operating the same, the vertical-type semiconductor device includes a single-crystalline semiconductor pattern having a pillar shape provided on a substrate, a gate surrounding sidewalls of the single-crystalline semiconductor pattern and having an upper surface lower than an upper surface of the single-crystalline semiconductor pattern, a mask pattern formed on the upper surface of the gate, the mask pattern having an upper surface coplanar with the upper surface of the single-crystalline semiconductor pattern, a first impurity region in the substrate under the single-crystalline semiconductor pattern, and a second impurity region under the upper surface of the single-crystalline semiconductor pattern. The vertical-type pillar transistor formed in the single-crystalline semiconductor pattern may provide excellent electrical properties. The mask pattern is not provided on the upper surface of the single-crystalline semiconductor pattern in the second impurity region, to thereby reduce failures of processes.

Method of manufacturing a vertical-type semiconductor device and method of operating a vertical-type semiconductor device

Methods of forming patterns of a semiconductor device are provided. The methods may include forming a hard mask film on a semiconductor substrate. The methods may include forming first and second sacrificial film patterns that are spaced apart from each other on the hard mask film. The methods may include forming a first spacer on opposing sidewalls of the first sacrificial film pattern and a second spacer on opposing sidewalls of the second sacrificial film pattern. The methods may include removing the first and second sacrificial film patterns. The methods may include trimming the second spacer such that a line width of the second spacer becomes smaller than a line width of the first spacer. The methods may include forming first and second hard mask film patterns by etching the hard mask film using the first spacer and the trimmed second spacer as an etch mask.

Methods of forming patterns of a semiconductor device

The present invention relates to a novel use of herbal extracts in a pharmaceutical composition for prevention and treatment of nephritis and, more particularly, to a pharmaceutical composition and a health functional food for prevention and/or treatment of nephritis that contains at least one herbal extract selected from the group consisting of a Crataegi Fructus extract, a Cinnamomi Cortex extract, a Prunella Spica extract, and an Equiseti Herba extract, a method for prevention and/or treatment of nephritis using the herbal extract, and a use of the herbal extract in preparation of a composition for prevention and/or treatment of nephritis. The herbal extract has a good therapeutic effect for nephritis on a nephritis model of which the nephritis is induced by a drug such as gentamicin, cisplatin, etc., and a good inhibitory activity on the growth of mesangial cells in kidneys, thereby providing a very useful means for prevention and/or treatment of nephritis.

Pharmaceutical composition containing herbal extract for prevention or treatment of nephritis

A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.

Semiconductor devices semiconductor pillars and method of fabricating the same

A use an extract ofor a combined extract ofandas an active ingredient for preventing and/or treating periodontal disease is provided. The extract ofor a combined extract ofandhas activities to stimulate anti-inflammation, osteoblast differentiation and alveolar bone regeneration, and to prevent the alveolar bone destruction, thereby being effective for the prevention and/or treatment of periodontal disease.

Preventing or treating periodontal diseases by herbal extract

In a semiconductor device, and a method of manufacturing thereof, the device includes a substrate of single-crystal semiconductor material extending in a horizontal direction and a plurality of interlayer dielectric layers on the substrate. A plurality of gate patterns are provided, each gate pattern being between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of single-crystal semiconductor material extends in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns, a gate insulating layer being between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

Vertical-type non-volatile memory devices

A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Semiconductor devices having contact plugs with stress buffer spacers and methods of fabricating the same

A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

Method of manufacturing vertical semiconductor device

A method of fabricating a semiconductor integrated circuit includes forming a first dielectric layer on a semiconductor substrate, patterning the first dielectric layer to form a first patterned dielectric layer, forming a non-single crystal seed layer on the first patterned dielectric layer, removing a portion of the seed layer to form a patterned seed layer, forming a second dielectric layer on the first patterned dielectric layer and the patterned seed layer, removing portions of the second dielectric layer to form a second patterned dielectric layer, irradiating the patterned seed layer to single-crystallize the patterned seed layer, removing portions of the first patterned dielectric layer and the second patterned dielectric layer such that the single-crystallized seed layer protrudes in the vertical direction with respect to the first and/or the second patterned dielectric layer, and forming a gate electrode in contact with the single-crystal active pattern.

Semiconductor integrated circuit device and a method of fabricating the same

Growing community of inventors

Yongin-si, South Korea

Jong-Wook Lee