Samsung Electronics Co., Ltd.

Ace Medical Co., Ltd.

Samsung Display Co., Ltd.

Samsung Mobile Display Co., Ltd.

Hyundai Motor Company

Korea Advanced Institute of Science and Technology

Dpi Solutions, Incorporated

Jong-woo Lee

Seung-hyun Oh

Jae-hoon Lee

Si-Bum Jun

Chilun Lo

Jae-Hyun Lim

Thomas Byung-Hak Cho

Thomas Byunghak Cho

Barosaim Sung

Byung-ki Han

Ji-Young Lee

Young-Min Kim

Jong-Soo Lee

Jae-kwon Kim

Tae-Seung Kim

Joong-Ho Lee

Ho Seok Lee

Pil-Sung Jang

Byung-Hak Cho

Su-Seob Ahn

Tae-Hwan Jin

Shin-Chul Kim

Jong-mi Lee

Woo-jin Jang

Won-Kyu Kwak

Hee-Tak Kim

Joon-Young Park

Hee-Dong Kim

Ji-hyeon Kweon

Hyun-Suk Min

Kwan-Woo Song

Jong-gu Jeon

Dong-Yun Hawng

Jong-won Han

Hyun-Nam Yoon

Seok-myong Kang

Jae-Kwon Kim

Hyun-wook Bae

Dong-Seok Kim

Chul-Hwan Kim

Jung-Ki Park

Gye-Young Lee

Seung-jin Kim

Seok-hoon Choi

Yong-in Lee

Shinichi Hisatomi

So-won Sheen

Sung-min Park

Heui-Sam Kwag

Yoon-suk Lee

Young-gi Min

Soon-Hyung Gwon

Pil-sung Jang

Shi-Joon Sung

Seung-Jin Kim

Manthena Vamshi

Byung-Ki Han

Soon-won Lee

Min-gyu Jo

Min-Gyu Jo

Yang-hun Lee

Sang-cheol Moon

Kyoung-Han Park

A receiver includes an amplification block supporting carrier aggregation (CA). The amplification block includes a first amplifier circuit configured to receive a radio frequency (RF) input signal at a block node from an outside source, amplify the RF input signal, and output the amplified RF input signal as a first RF output signal. The first amplifier circuit includes a first amplifier configured to receive the RF input signal through a first input node to amplify the RF input signal, and a first feedback circuit coupled between the first input node and a first internal amplification node of the first amplifier to provide feedback to the first amplifier.

Radio frequency (RF) integrated circuit performing signal amplification operation to support carrier aggregation and receiver including the same

Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for further translating the frequencies of the receive signal in the digital domain.

Carrier aggregated signal transmission and reception

A radio frequency (RF) integrated circuit is provided. The RF integrated circuit supports carrier aggregation and includes first receiving circuits and a first shared phase locked loop circuit that provides a first frequency signal of a first frequency to the first receiving circuits. One of the first receiving circuits includes an analog to digital converter (ADC) and a digital conversion circuit. The ADC converts an RF signal received by the one of the first receiving circuits to a digital signal by using the first frequency signal. The digital conversion circuit generates a digital baseband signal by performing frequency down conversion on the digital signal.

Radio frequency integrated circuit supporting carrier aggregation and wireless communication device including the same

A clock generation apparatus includes a pulse generator configured to generate a pulse signal and a selection signal using a reference clock signal, a delay line circuit, a switch and a controller. The delay line circuit selects, as an input signal to a delay path, the pulse signal or a fed back portion of a delay clock signal at an output of the delay path, where the selection is based on the selection signal; and thereby generates the delay clock signal. The switch switches a first voltage or a second voltage to the delay line circuit for its operation, where the first voltage further provides power to the pulse generator. The second voltage is generated based on a phase difference between the reference clock signal and the delay clock signal. The controller generates a switch control signal based on a frequency of the delay clock signal.

Method and apparatus for generating clock

A method and device for determining a distance are provided. The method includes determining a first binocular distance between two eyes of a user by using a first image captured through a camera of the device, determining a second binocular distance between the two eyes of the user by using a second image captured through the camera, determining a distance from the camera to the two eyes of the user based on the first binocular distance and the second binocular distance, and providing an image to a display of the device, the image converted according to the distance from the camera to the two eyes of the user.

Method and device for determining distance

Provided are a radio-frequency integrated chip (RFIC) and a wireless communication device including the RFIC. An RFIC configured to receive a carrier aggregated receive signal having at least first and second carrier signals may include first and second carrier receivers configured to generate, from the receive signal, first and second digital carrier signals, respectively. A phase-locked loop (PLL) may output a first frequency signal having a first frequency to the first carrier receiver and the second carrier receiver. The first and second carrier receivers may include first and second analog mixers, respectively, for translating frequencies of the receive signal, using the first frequency signal and the second frequency signal, respectively. Each of the first and second carrier receivers may further include a digital mixer for farther translating the frequencies of the receive signal in the digital domain.

A variable capacitor is provided. The variable capacitor includes a plurality of capacitor segments. The plurality of capacitor segments are connected in parallel within the variable capacitor. When a plurality of candidate capacitances allowable to the variable capacitor according to a connection state of the plurality of capacitor segments connected in parallel are sorted in a magnitude sequence, the plurality of candidate capacitances form a geometric series. The variable capacitor is used for a Voltage Controlled Oscillator (VCO), and the VCO is used for a Phase Locked Loop (PLL).

Voltage controlled oscillator using variable capacitor and phase locked loop using the same

A method for issuing an access token of a device by a control point is provided. The method includes transmitting a search request message to the device, receiving, from the device, a search response message including first information indicating a type of the device, requesting access token issuance to the device using first information and second information, the second information including additional information about the device, and receiving the access token from the device. The second information may include model information about the device.

Method and apparatus for issuing and getting access token of device

A variable feedback gain delta modulator includes group of capacitors commonly connected to a first terminal and are respectively classified into a first capacitor group and a second capacitor group; a comparator for sequentially generating n-bit digital output signals based on a voltage of the first terminal; and a switch group including switches respectively connected to the capacitors, wherein the switches are respectively classified into a first switch group and a second switch group respectively connected to the first capacitor group and the second capacitor group, and the first switch group and the second switch group respectively operate according to a first control signal and a second control signal that are determined based on the n-bit digital output signals and the variable feedback gain.

Delta modulator with variable feedback gain, analog-to-digital converter including the delta modulator, and communication device including the delta modulator

A reference voltage circuit is provided. The reference voltage circuit includes a first current bias circuit including a first node; a second current bias circuit including a plurality of NMOS transistors and a second node, and an amplifier configured to output a reference voltage having same value as the second voltage. The plurality of NMOS transistors include a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is connected to the first node, and the plurality of NMOS transistors are connected to the second node and configured to perform a sub-threshold operation based on a first voltage of the first node so that a second voltage is generated at the second node.

Terminal device including reference voltage circuit

The present invention relates to an apparatus and a system for controlling an amount of medicine or fluid injection through falling due to potential energy of the fluid. For example, the present invention can automatically adjust an injection rate of a medicine injected into a patient by controlling an opening/closing degree of a medicine hose by using a driving element driven by electric power according to a comparison of the number of drops with a predetermined value. An apparatus for realizing the method includes an accommodating case for accommodating a connecting portion for connecting a fluid, a detection unit for detecting the number of drops, a control unit for comparing the information detected by the detection unit, and a driving element for opening and closing a passage of the medicine hose based on the contents analyzed by a control unit.

Method and apparatus for automatically adjusting injection rate through falling

The present disclosure provides a method and a phase lock detection apparatus for detecting whether a phase of an output signal is locked to the phase of a reference signal. The apparatus includes a first divider that individually frequency-divides first and second pulse signals, a phase frequency detector that outputs third and fourth pulse signals that correspond to a phase difference between the frequency-divided first and second pulse signals, a second divider that individually frequency-divides the third and fourth pulse signals, and a determiner that determines whether a phase of the second pulse signal is locked, based on the frequency-divided third and fourth pulse signals.

Apparatus and method for detecting phase lock in an electronic device

A test socket is provided that includes a base material including an insulating elastic material and a conductive portion extending through the base material in a thickness direction of the base material, wherein the conductive portion includes a plurality of conductive particle structures arranged in the thickness direction of the base material, and each of the plurality of conductive particle structures includes a plurality of conductive particles having at least one insulating wire and/or at least one conductive wire extending from a surface of the conductive particle, bonded with a material having a functional group.

Test socket for testing semiconductor chip package and method of manufacturing the same

Growing community of inventors

Seoul, South Korea

Jong-woo Lee