Samsung Electronics Co., Ltd.

Samsung Corporation

Jong-won Kim

Young-Woo Park

Jae-Goo Lee

Jin-kyu Park

Yong-Hoon Son

Yong-Seok Kim

Yong-jin Kim

Chang-seok Kang

Jae-Duk Lee

Jae-pil Shin

Tae-hyun Kim

Joon-Hee Lee

Kyung-Hyun Kim

Hyo-Jin Kim

Sung-Hoi Hur

Jong-Ho Park

Ho-Yong Jung

Ki-Chul Park

Giu-Yeol Kim

Hong-uk Woo

Tae-heon Kim

Yong-hyeon Kim

Dong-yun Shin

Phil-Ouk Nam

Yeon-Sil Sohn

Young-jin Choi

Jin-hyun Shin

Jin-I Lee

Jae-sung Kang

Won-Bong Jung

Won-Young Chung

Ho-Joon Lee

Kwang-Chul Park

Kyu-Baik Chang

Ha-young Yoon

Si-woo Kim

Byeong-Ju Kim

Jun-young Ko

Po-seong Park

Ming Jin

Chang-Woo Kang

Hun-Seop Jeong

Patterns in an integrated circuit may be evaluated, and a semiconductor device may be fabricated based on the evaluation. The evaluation may include a extracting and superimposing first patterns corresponding to design patterns of the same shape from input layout data generated based on inspecting the integrated circuit, generating distribution data of the first patterns based on the superimposed first patterns, determining an evaluation contour of the design patterns based on an evaluation condition and the distribution data, and generating output layout data based on replacing the first patterns with second patterns each having the evaluation contour. Weak points in the integrated circuit may be detected based on the output layout data. The fabricating may include selectively incorporating an integrated circuit into a semiconductor device based on a determination that the integrated circuit includes less than a threshold quantity and/or threshold concentration of weak points.

Systems and methods of fabricating semiconductor devices

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

Non-volatile memory device

A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.

Nonvolatile memory device and a method for fabricating the same

A method of detecting stress of an integrated circuit including first and second patterns formed from different materials may comprise: determining one or more stress detection points of the first pattern; dividing a region including a first stress detection point of the one or more stress detection points into a plurality of divided regions; calculating areas of the second pattern at the divided regions; and/or detecting a stress level applied to the first stress detection point of the first pattern by the second pattern based on the areas of the second pattern at the divided regions.

Methods of detecting stresses, methods of training compact models, methods of relaxing stresses, and computing systems

A voltage generator that prevents latch-up includes: a charge pump circuit that is controlled by first through third enable signals, boosts an internal power voltage generated from an external power voltage, and generates first through fourth voltages; a detector that detects the first through third voltages and generates first through third flag signals that go logic high when the first through third voltages reach predetermined respective voltage levels and maintain logic low when the voltages do not reach the predetermined respective voltage levels; and a charge pump controller that receives the first through third flag signals, and generates the first through third enable signals to have the first through fourth voltages sequentially generated. The voltage generator can prevent latch-up that may occur in a boosting mode or in a normal operation mode.

Voltage generator that prevents latch-up

A method and apparatus for a wireless network to maintain a QOS is provided. The apparatus includes a resource calculating unit which calculates resources needed to transmit packets if a transmission rate of a network changes, a comparing unit which compares the calculated resources and resources allotted by an access point of the network; and a control unit which determines whether to request additional resources by using a result of the comparison by the comparing unit.

Wireless network device and resource allotting method for the same

A nonvolatile memory device may include a substrate having a cell region, and a cell device isolation layer on the cell region of the substrate to define a cell active region. A floating gate may include a lower floating gate and an upper floating gate sequentially stacked on the cell active region, and a tunnel insulation pattern may be between the floating gate and the cell active region. A control gate electrode may be on the floating gate, and a blocking insulation pattern may be between the control gate electrode and the floating gate. More particularly, the upper floating gate may include a flat portion on the lower floating gate and a pair of wall portions extending upward from both edges of the flat portion adjacent to the cell device isolation layer. Moreover, a width of an upper portion of a space surrounded by the flat portion and the pair of wall portions may be larger than a width of a lower portion of the space. Related methods are also discussed.

Non-volatile memory devices having floating gates

An apparatus for cutting tie bars of semiconductor packages unloads the semiconductor packages by continuously blowing air against the side of the packages after the tie bars are cut and the semiconductor packages are separated from lead frames. The packages are blown into a guide track which feeds into a storage tube. As a result, damage to the packages due to mechanical abrasion which may result from unloading with a pusher bar is prevented. Furthermore, the time required for unloading the semiconductor packages is reduced.

Apparatus for cutting tie bars of semiconductor packages

Growing community of inventors

Hwaseong-si, South Korea

Jong-won Kim