Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Jong-Wha Chong

Myung-Soo Jang

Cheol-Jon Jang

Jae-Hwan Kim

Jae-Rim Lee

Min-Ho Kim

Jung-Min Choi

Min-Beom Kim

Ji-Ho Song

Byung-Gyu Ahn

Wen Rui Li

Kyung-In Cho

A method for manufacturing a semiconductor device can reduce congestion across wires while reducing a wire length. The method includes determining a first TSV candidate region in a first die and determining a second TSV candidate region in a second die parallel to the first die. The method also includes determining a first bound region. The first bound region includes a horizontal location of a first pin of the first die and a horizontal location of a second pin of the second die. The method additionally includes calculating an area from overlapped regions between the first bound region and each of the first TSV candidate region and the second TSV candidate region, and performing routing for connecting the first pin and the second pin to each other based on the calculated area.

Method of manufacturing semiconductor device

To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.

Method of designing power supply network

A method of designing arrangement of through silicon vias (TSVs) in a stacked semiconductor device is provided The method includes: determining a plurality of TSV candidate grids representing positions, into which the TSVs are insertable, in each of a plurality of semiconductor dies stacked mutually and included in a stacked semiconductor device; creating a plurality of path graphs representing linkable signal paths for a plurality of signals transmitted through the stacked semiconductor device, respectively, based on the TSV candidate grids; determining initial TSV insertion positions corresponding to shortest signal paths for the signals based on the path graphs; and determining final TSV insertion positions by verifying the initial TSV insertion positions so that a plurality of signal networks corresponding to the shortest signal paths for the signals have routability.

Method of designing arrangement of TSV in stacked semiconductor device and designing system for arrangement of TSV in stacked semiconductor device

Provided are a method of updating a tap coefficient of a channel equalizer while reducing the number of calculations and the divergence, and a circuit arranged and configured to execute the method. The method includes evaluating whether or not an error of the channel equalizer converges within a range of a threshold of visibility and determining the status of a control signal to select whether the tap coefficient of the channel equalizer will be updated using a least mean square (LMS) algorithm or a Kalman algorithm, wherein the LMS algorithm is the default error correction means and the Kalman algorithm is utilized when the control signal indicates the presence of a training signal.

Method and circuit for updating a tap coefficient of a channel equalizer

Growing community of inventors

Seoul, South Korea

Jong-Wha Chong