Electronics and Telecommunications Research Institute

Jong Tae Moon

Yong Sung Eom

Kwang-Seong Choi

Hyun-cheol Bae

Kwang Seong Choi

Sangwon Oh

Keonsoo Jang

Jong-Hyun Lee

Chi Hoon Jun

Sang Choon Ko

Je Ha Kim

Young Shik Kang

Yong Duck Chung

Ho Gyeong Yun

Min Soo Kim

Jong Hyun Lee

Hyun Kyu Yu

Dong Suk Jun

Heung Woo Park

Min Ji Lee

Moo Jung Chu

Byung Seok Choi

Jong-Moon Park

Jung Hyun Noh

A pattern-forming method for forming a conductive circuit pattern, the pattern-forming method including the steps of: preparing a pattern-forming composition composed of: Cu powder; solder particles for electrically coupling the Cu powder; a polymer resin; a deforming agent that is selected from among acrylate oligomer, polyglycols, glycerides, polypropylene glycol, dimethyl silicon, simethinecone, tributyl phosphare, and polymethylsiloxane, and that increases bonding force between the Cu powder and the solder particles; a curing agent; and a reductant; forming a circuit pattern by printing the pattern-forming composition on a substrate; heating the circuit pattern at a temperature effective to cure the pattern-forming composition and provide the conductive circuit pattern; and electrolytically plating a metal layer onto the conductive circuit pattern. A circuit pattern having superior conductivity is formed at low cost.

Pattern-forming method for forming a conductive circuit pattern

Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.

Composition and methods of forming solder bump and flip chip using the same

A piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.

Method of manufacturing a piezoelectric micro energy harvester

Disclosed is a silicon interposer that can reduce the entire area of a semiconductor package and increase the degree of integration by forming inductors at a lower part in addition to an upper part of a silicon substrate. The silicon interposer includes a silicon substrate, an upper inductor layer formed at the upper part of the silicon substrate and a lower inductor layer formed at the lower part of the silicon substrate.

Silicon interposer including backside inductor

Disclosed is a piezoelectric micro energy harvester and manufacturing method thereof, the method including: forming an insulation film on a substrate; patterning the insulation film and forming an electrode pad pattern, a center electrode pattern, and a side electrode pattern; forming an open cavity at an inside of the substrate for suspension of the center electrode pattern and the side electrode pattern; disposing a conductive film on the electrode pad pattern, the center electrode pattern, and the side electrode pattern and forming electrode pads, a center electrode, and a side electrode; and forming a piezoelectric film so as to cover a space between the center electrode and the side electrode and upper surfaces of the center electrode and the side electrode.

Piezoelectric micro energy harvester and manufacturing method thereof

Disclosed is a vacuum wafer level packaging method for a micro electro mechanical system device, including: forming a plurality of via holes on an upper wafer for protecting a micro electro mechanical system (MEMS) wafer; forming at least one metal layer on inner walls of the plurality of via holes and regions extended from the plurality of via holes; arranging and bonding the upper wafer and the MEMS wafer at atmospheric pressure; applying solder paste to the regions extended from the plurality of via holes; filling a solder in the plurality of via holes by increasing the temperature of a high-vacuum chamber to melt the solder paste; and changing the solder in the plurality of via holes to a solid state by lowering the temperature of the high-vacuum chamber.

Vacuum wafer level packaging method for micro electro mechanical system device

Provided is a method and structure for bonding a flip chip while increasing the manufacturing yield. In the method, solder bumps are formed on first electrodes and/or second electrodes disposed on first and second substrates, respectively. In addition, the first and second electrodes are arranged to face each other with a second resin including spacer balls being disposed between the first and second substrates. In addition, while flowing the second resin, the first and second substrates are pressed until the distance between the first and second substrates is decreased smaller than diameter of the spacer balls so as to connect the solder bumps between the first and second electrodes.

Method and structure for bonding flip chip

Provided is an electronic device that includes an LTCC inductor including a first sheet disposed on a substrate and including a first conductive pattern, a second sheet disposed on the first sheet and including a second conductive pattern, and a via electrically connecting the first conductive pattern to the second conductive pattern, and a spacer disposed on a lower surface of the first sheet to provide an air gap between the substrate and the first sheet, wherein the first conductive pattern is exposed out of the lower surface of the first sheet.

Electronic device including LTCC inductor

A method for fabricating a semiconductor package, includes the steps of forming a first terminal at a first substrate; mixing a polymer resin and solder particles to provide a mixture; covering at least one of an upper surface and side surfaces of the first terminal with the mixture; and heating the first substrate at a temperature higher than a melting point of the solder particles of the mixture to form a solder layer that covers the at least one of an upper surface and a side surface of the first terminal. The solder particles flow or diffuse toward the terminal in the heated polymer resin to adhere to at least some of the exposed surfaces of the terminal thereby forming the solder layer. The solder layer improves the adhesive strength between the terminals of the semiconductor chip and the substrate in the subsequent flip chip bonding process.

Method for fabricating a semiconductor package

Provided are a wafer level package in which a communication line can be readily formed between an internal device and the outside of the package, and a method of fabricating the wafer level package. The wafer level package includes a first substrate having a cavity in which a first internal device is disposed, an Input/Output (I/O) pad formed on the first substrate and electrically connected with the first internal device, a second substrate disposed over the first substrate and from which a part corresponding to the I/O pad is removed, and a solder bonding the first and second substrates. According to the wafer level package and the method of fabricating the same, upper and lower substrates are sawed to different cutting widths, or a hole is formed in the upper substrate, such that a communication line of an internal device can be readily formed without a via process which penetrates a substrate. Therefore, in comparison with a conventional wafer level package fabricated using the via process, it is possible to simplify a fabrication process and reduce production cost.

Wafer level package and method of fabricating the same

Provided are an inductor, which is vertically formed, and an electronic device having the inductor, and more particularly, an inductor capable of minimizing loss of a surface area and accomplishing high efficiency impedance by vertically forming the inductor in a plurality of insulating layers, and an electronic device having the same. The inductor includes a plurality of conductive lines disposed in the insulating layers; and vias vertically formed in the insulating layers to electrically connect the plurality of conductive lines. When a board or an electronic device including an inductor proposed by the present invention is manufactured, the inductor can occupy a minimum area in the electronic device or board while providing high inductance. In particular, the surface area of the electronic device or board occupied by the inductor can be remarkably decreased to reduce manufacturing costs.

Vertically formed inductor and electronic device having the same

Provided is an optical module used in a communication system employing a radio over fiber (ROF) technology delivering a radio frequency (RF) signal through an optical fiber. The optical module includes: an optical device; a signal line for transporting a radio frequency (RF) signal input from an external circuit to the optical device; and a resistor separately disposed from the signal line and having one end connected with the optical device, wherein the input impedance seen from the signal line is matched by the resistor. A bias voltage supplied to operate the optical device is applied through an inductor connected to the signal line between the optical device and a filter. Here, the filter formed by a pattern of the signal line prevents the bias voltage from being supplied to the external circuit. In order to amplify the RF signal input from the external circuit, an amplifier may be connected between the external circuit and the filter.

Growing community of inventors

Gyeryong-si, South Korea

Jong Tae Moon