Samsung Electronics Co., Ltd.

Samsung Display Co., Ltd.

Jong-Soo Yoon

Woon-Yong Park

Mun-Pyo Hong

Dong-Gyu Kim

Bum-Ki Baek

Jang-Soo Kim

Chang-Oh Jeong

Jeong-Young Lee

Kwon-Young Choi

Jun-Hyung Souk

Woon-yong Park

Sung-Wook Huh

Dong-Ho Lee

Byoung-Sun Na

Young-Joon Rhee

Sung-Wook Hao

Hyung-Guel Kim

Yong-Kyu Jang

Yea-Sun Yoon

Jin-Kwan Kim

Doug-Gyu Kim

Disclosed are a system and a method for analyzing and utilizing intellectual property information. The method comprises the steps of registering search strategy formulas for extracting intellectual property (IP) information; accessing and searching Internet websites that provide IP information based on the registered search strategy formulas, and extracting first IP information according to the search; placing the first IP information in a standard form and performing a first storage operation of the first IP information, and transmitting the converted IP information to research center PCs; determining whether a request for detailed information has been made from the research center PCs, and if it has, accessing the Internet websites and extracting second IP information corresponding to the first IP information; and placing the second IP information in a standard form and performing a second storage operation of the converted IP information, and transmitting the converted IP information to the research center PCs. The system comprises an IP information extraction unit for extracting IP information according to the operation of software from at least one on-line IP information DB; an IP information analyzing unit for controlling the operation of the software, receiving the extracted IP information and storing the same together with data containing predetermined opinion contents, and outputting the IP information; and an E-mail receiving/transmitting unit for transmitting the IP information received from the IP information analyzing unit to research center PCs, and receiving feedback of data containing opinion contents from the research center PCs.

System and method for analyzing and utilizing intellectual property information

A method of manufacturing a thin film transistor array panel is provided, the method includes: forming a gate line on an insulating substrate; forming a gate insulating layer; forming a semiconductor layer; forming a data conductive layer including a data line and a drain electrode; depositing a passivation layer; forming a photoresist including a first portion located on an end portion of the gate line, a second portion thicker than the first portion and located on the drain electrode, and a third portion thicker than the second portion; exposing a portion of the passivation layer under the second portion of the photoresist and a portion of the gate insulating layer under the first portion of the photoresist by etching using the photoresist as an etch mask; forming first and second contact holes exposing the drain electrode and the end portions of the gate line, respectively; and forming a pixel electrode connected to the drain electrode through the first contact hole.

Thin film transistor array panel and manufacturing method thereof

A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area. The passivation layer and the underlying layers are etched through the photoresist pattern to form a semiconductor pattern and contact windows. A pixel electrode, a supplemental gate pad and a supplemental data pad are then formed of indium tin oxide or indium zinc oxide. The gate and data line assemblies may be formed with a single layered structure. A black matrix and a color filter may be formed at the structured substrate before forming the pixel electrode, and an opening portion may be formed between the pixel electrode and the data line to prevent possible short circuits.

Thin film transistor array substrate for a liquid crystal display

The invention is directed to simultaneously etching thin films to different uniform depths depending on positions by using a photoresist pattern having different thickness depending on positions as an etch mask in order to form a contact hole for a gate pad along with at least one other layer, or a data wire and a semiconductor pattern, via a single photolithography step.

Thin film transistor array panels for a liquid crystal display and a method for manufacturing the same

Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer. Next, the exposed portions of conductor layer are removed by wet etch or dry etch, and thereby the underlying ohmic contact layer is exposed. Then the exposed ohmic contact layer and the underlying semiconductor layer are removed by dry etching along with the first portion of the photoresist layer. The residue of the photoresist layer is removed by ashing. Source/drain electrodes are separated by removing the portion of the conductor layer at the channel and the underlying ohmic contact layer pattern. Then, the second portion of the photoresist layer is removed, and red, green, and blue color filters, a pixel electrode, a redundant gate pad, and a redundant data pad are formed.

Thin film transistor array panel and methods for manufacturing the same

Disclosed is liquid crystal display, a substrate for a liquid crystal display and a method for manufacturing the substrate. The substrate comprises a transparent electrode formed on the insulating substrate, and a black matrix formed on the transparent electrode and performing the function also of protrusions. The method comprises the steps of forming a transparent electrode on a substrate, forming a black matrix layer, depositing a photosensitive material on the black matrix layer to form a photosensitive layer, patterning the photosensitive layer, and etching the black matrix layer using the photosensitive layer as a mask. The liquid crystal display comprises, among other things, redundant data lines formed on a same layer as the pixel electrodes; an insulating second substrate provided opposing the first substrate at a predetermined distance; a common electrode formed on the second substrate; and a protrusion pattern formed on the common electrode in at least regions corresponding to the positions of the redundant data lines, the protrusion pattern being made of an insulating material.

Liquid crystal display and substrate thereof

In an LCD apparatus () having simplified structure and improved luminance, a light supplying unit () supplies an LCD panel () with red light during a time corresponding to one-third of a frame, green light during the time and blue light during the time. A light reflective-transmissive unit is disposed between the light supplying unit () and the LCD panel assembly () to transmit the red light, the green light and the blue light and to reflect an external light from exterior of the LCD panel assembly (). The LCD apparatus displays an image by means of white light as well as red light, green light and blue light, thereby improving luminance and simplifying structure.

Liquid crystal display apparatus

A gate conductor including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between the to be formed source electrode and drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data conductor including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for a storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon. A passivation layer made of acryl-based organic material having excellent planarization characteristic is formed thereon. A pixel electrode, an auxiliary gate pad and an auxiliary data pad connected to the drain electrode, the gate pad and the data pad via contact holes, respectively, are formed on the passivation layer. The contact hole exposing the drain electrode is located within the aperture.

Thin film transistor array panel for display and manufacturing method thereof

A conductive layer, including a lower layer made of refractory metal such as chromium, molybdenum, and molybdenum alloy and an upper layer made of aluminum or aluminum alloy, is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode on a substrate. At this time, the upper layer of the gate pad is removed using a photoresist pattern having different thicknesses depending on position as etch mask. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially formed. A conductive material is deposited and patterned to form a data wire including a data line, a source electrode, a drain electrode, and a data pad.

A method of fabricating a thin film transistor array substrate for a liquid crystal display includes the step of forming a gate line assembly with gate lines, gate electrodes and gate pads. After laying a plurality of layers on the substrate, a photoresist film is deposited onto the layers. The photoresist film is first exposed to light at a first light exposing unit, and secondly exposed to light at a second light exposing unit such that the photoresist film has three portions of different thickness. The photoresist pattern, and some of the underlying layers are etched to form a data line assembly, a semiconductor pattern, and an ohmic contact pattern. The data line assembly includes data lines, source and drain electrodes, and data pads. The remaining photoresist film is removed, and a protective layer is formed on the substrate. The protective layer is etched together with the gate insulating layer to form first to third contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Pixel electrodes, subsidiary gate and data pads are then formed.

Photolithography method for fabricating thin film

Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched. After depositing a passivation layer, a opening is formed by using the fourth mask and the exposed semiconductor layer through the opening is etched to separate the semiconductor layer under the adjacent data line.

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Cheonan, South Korea

Jong-Soo Yoon