Samsung Electronics Co., Ltd.

Yonsei University

Jong-Soo Seo

Beak-Hyung Cho

Woo-Yeong Cho

Du-Eung Kim

Jae-Hyeon Bae

Young-Kug Moon

Eun-jung Yun

Hak-ju Lee

Jong-Hyeuk Lee

Sung-min Kim

Won-Seok Lee

Byung-seo Kim

Won-Kyu Paik

Hak-Jin Kim

Soon-Ki Jo

Jong-Ho Lee

Kwang-Jin Lee

Sang-Boh Yun

Byung-Gil Choi

Dongjin Lee

Joo-Hyun Lee

Young-ho Oh

Myeon-Kyun Cho

Sung-Hwan Kim

Jun-Soo Bae

Min-Ho Kim

Sung-Soo Hwang

Kwang-Ho Kim

Sung-Yoon Jung

Young-Goo Ko

Hyuck-Sun Kwon

Taek-Sung Kim

Bo-Tak Lim

Su-Yeon Kim

Dae-Young Park

Ki-ho Shin

Janghwan Kim

Hwan-Jin Yong

Donghyun Song

Tae-Hwa Yoo

Byungse So

Kyoungsub Oh

Kwan-Jong Park

Jong-Kyung Kim

Byungjin Ahn

Jong-gyu Park

Jin-Yong Choi

Hak-jin Kim

Ik-chul Kim

Jae Shin Han

Jong Seob Baek

An apparatus and a method for transmitting uplink information in a broadcasting system are provided. A repeater of a mobile broadcasting system includes a plurality of transmitting stations each transmitting a broadcast signal for at least one broadcast service, a plurality of terminals receiving the broadcast signal for the at least one broadcast service through at least one transmitting station among the transmitting stations, and the repeater, the repeated being coupled between the plurality of transmitting stations and the plurality of terminals. The repeater includes a receiving unit configured to receive uplink information from the terminals, a control unit configured to classify the received uplink information by broadcast service and to create uplink information per broadcast service, and a transmitting unit configured to transmit the created uplink information to at least one corresponding transmitting station.

Apparatus and method for transmitting uplink information in a broadcasting system

A transmitting apparatus, a receiving apparatus and controlling these apparatuses with regard to antenna identification information are provided. The transmitting apparatus includes: a frame generator configured to generate a plurality of frames which include a preamble symbol and a data symbol; and a transmitter configured to group a plurality of sub-carriers for the plurality of frames into a plurality of groups, insert in the plurality of frames antenna identification information controlling a sum of phase differences between the plurality of groups, calculated based on identification information about at least one external antenna of the transmitting apparatus, to be lowered than a predetermined threshold value, and transmit the plurality of frames in which the antenna identification information is inserted.

Transmitter, receiver, and methods for controlling thereof

A method and an apparatus for transmitting and receiving a response signal in a wireless communication system are provided. In a method for transmitting a response signal in a broadcasting system, Acknowledgement (ACK) information for uplink packet data for each user is generated. A symbol and a subcarrier which will transmit the ACK information for each user inside a transmission frame are determined. ACK transmission related information is transmitted via a control channel inside the transmission frame. The ACK information for each user is transmitted via the determined symbol and subcarrier inside the transmission frame.

Method and apparatus for transmitting/receiving response signal in wireless communication system

A user device is provided. The device includes a main power supply, and an auxiliary power supply. The main power supply provides a main power. The auxiliary power supply cuts off the main power according to a power level of the main power supply and provides an auxiliary power upon Sudden Power-Off (SPO).

Auxiliary power supply and user device including the same

A method and device for decoding in a differential orthogonal space-time block coded system are disclosed. The disclosed method includes: (a) receiving signals from a transmitter during a particular time slot segment, where the signals are encoded by differential orthogonal space-time block coding; (b) transforming to reception signals for two sub-systems by using a sum operation and a difference operation of the signals received in step (a), where the transformed reception signals for the two sub-systems maintain an orthogonality of an orthogonal space-time block coded system; and (c) performing decoding using the reception signals for the two sub-systems transformed in step (b). The method provides the advantage of lowering the level of operational complexity for decoding in a communication system that employs differential orthogonal space-time block coding.

Method and device for decoding in a differential orthogonal space-time block coded system

Provided are a receiver and a method for detecting a signal in a multiple antenna system. The receiver includes a filter coefficient calculator and a signal detector. After separating a first signal portion and a second signal portion, the filter coefficient calculator calculates an MMSE filter coefficient using a Matrix Inversion Lemma such that an inverse matrix of the first signal portion has a predetermined constant value regardless of a repetition signal detection process. The signal detector detects a relevant transmission signal from an interference-removed reception signal using the MMSE filter coefficient.

Receiver and method for detecting signal in multiple antenna system

In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

Semiconductor memory device with stacked memory cell and method of manufacturing the stacked memory cell

A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Variable resistance memory device and system thereof

Provided are an apparatus and method for allocating resources in a mobile communication system. The apparatus includes a modulating/coding unit for modulating transmission data of one or more users according to a predetermined modulation scheme and for outputting a complex signal; a 2-Dimensional (2D)/1-Dimensional (1D) converter for converting the complex signal into a 1D signal; and a re-modulator for reconstructing the 1D signal to a 2D signal and for allocating two components of the 2D signal to two different frequency bands.

Apparatus and method for allocating resources in mobile communication system

An apparatus and method for determining a pilot pattern in a Broadband Wireless Access (BWA) communication system are provided. In the pilot pattern determining method, an Orthogonal Frequency Division Multiplexing (OFDM) demodulator generates frequency-domain data by fast-Fourier-transform (FFT)-processing a received signal. A pilot pattern decider calculates a coherence bandwidth and a coherence time using subcarrier values received from the OFDM demodulator, and selects one of a plurality of pilot patterns according to the ratio of the coherence bandwidth to the coherence time.

Apparatus and method for determining pilot pattern in a broadband wireless access communication system

A phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit; a plurality of local bit lines, each of which being connected to a plurality of phase-change memory cells; and a plurality of column select transistors selectively connecting the global bit line with each of the plurality of local bit lines. Each column select transistor has a resistance that depends on distance from the write circuit and the read circuit.

Phase change random access memory device

A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

Variable resistance memory device

A phase change memory device is provided which includes a memory cell array including a plurality of memory cells, and a write driver for supplying a program current to the memory cell array through a global bitline. The memory cell array includes first and second cell regions, a first local bitline connected to the first cell region, a second local bitline connected to the second cell region, and a select region disposed between the first and second cell regions and supplying the program current supplied through the global bitline to the first and second local bitlines in response to a local select signal.

Phase change memory device and memory cell array thereof

In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

Semiconductor memory device with stacked control transistors

A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

Phase change memory device and method of driving word line thereof

Growing community of inventors

Hwaseong-si, South Korea

Jong-Soo Seo