Intel Corporation

Facebook, Inc.

Meta Platforms, Inc.

Jong Soo Park

Christopher J Hughes

Mikhail Smelyanskiy

Abdulkadir Utku Diril

Nadav Rotem

Daehyun Kim

Richard M Yoo

Rajesh M Sankaran

Rajat Agarwal

Sheng C Li

Berkin Akin

Tsung-Yuan Charles Tai

Ren Wang

Christian Maciocco

Andrew J Herdrich

Alexander W Min

Yen-Cheng Liu

Jr-Shian Tsai

Victor W Lee

Herbert H Hum

David A Koufaty

Zeshan A Chishti

Mesut A Ergin

Aamer Jaleel

Namakkal N Venkatesan

Adrian C Moga

Changkyu Kim

Subramanya R Dulloor

Chiachen Chou

Roman Dzhabarov

Christopher Dewan

Roman Levenstein

James Wesley Hegeman

James Kenneth Reed

Zhaoxia Deng

Alexander F Heinecke

Nadathur Rajagopalan Satish

Deborah T Marr

Asit K Mishra

Samantika S Sury

Doddaballapur N Jayasimha

Jonas Svennebring

Hongbo Rong

Ping Tak Peter Tang

Geoff Lowney

Andrew John Tulloch

Ganesh Bikshandi

Saleem Abdulrasool

Lingxiang Xiang

Michael A Anderson

Dong Hyuk Woo

Maxim Naumov

Vladimir S Petrov

Mostofa Ali Patwary

Narayanan Sundaram

Camilo A Moreno

Benjamin Ray

Jedrzej Jablonski

Daya Shankar Khudia

Disclosed embodiments relate to atomic memory operations. In one example, a method of executing an instruction atomically and with weak order includes: fetching, by fetch circuitry, the instruction from code storage, the instruction including an opcode, a source identifier, and a destination identifier, decoding, by decode circuitry, the fetched instruction, selecting, by a scheduling circuit, an execution circuit among multiple circuits in a system, scheduling, by the scheduling circuit, execution of the decoded instruction out of order with respect to other instructions, with an order selected to optimize at least one of latency, throughput, power, and performance, and executing the decoded instruction, by the execution circuit, to: atomically read a datum from a location identified by the destination identifier, perform an operation on the datum as specified by the opcode, the operation to use a source operand identified by the source identifier, and write a result back to the location.

Instructions for remote atomic operations

A processor includes a decode unit to decode an instruction indicating a source packed data operand having source data elements and indicating a destination storage location. Each of the source data elements has a source data element value and a source data element position. An execution unit, in response to the instruction, stores a result packed data operand having result data elements each having a result data element value and a result data element position. Each result data element value is one of: (1) equal to a source data element position of a source data element, closest to one end of the source operand, having a source data element value equal to the result data element position of the result data element; and (2) a replacement value, when no source data element has a source data element value equal to the result data element position of the result data element.

Data element rearrangement, processors, methods, systems, and instructions

Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

Processor and method implementing a cacheline demote machine instruction

The disclosed computer-implemented method may include compiling a neural network, and the compiling may include organizing an interconnected set of nodes in a series of layers, and for each node in each layer, assigning an associated activation of a plurality of activations. Each activation may output a respective tensor of a plurality of tensors. The compiling may also include allocating memory for the activations by determining a respective memory size for each activation, and based on the respective memory size for each activation, assigning a memory block in the neural network to the activation. The method may also include, after the allocating the memory for the activations, accessing the memory blocks to perform the plurality of activations and thereby execute the neural network. Various other methods, systems, and computer-readable media are also disclosed.

Static memory allocation in neural networks

The disclosed computer-implemented method may include (i) identifying a neural network that comprises an interconnected set of nodes organized in a set of layers represented by a plurality of matrices that each comprise a plurality of weights, where each weight represents a connection between a node in the interconnected set of nodes that resides in one layer in the set of layers and an additional node in the set of interconnected nodes that resides in a different layer in the set of layers, (ii) encrypting, using an encryption cipher, the plurality of weights, (iii) detecting that execution of the neural network has been initiated, and (iv) decrypting, using the encryption cipher, the plurality of weights in response to detecting that the execution of the neural network has been initiated. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for protecting neural network weights

The disclosed computer-implemented method may include (1) identifying an artificial neural network comprising a set of nodes interconnected via a set of connections, and (2) training the artificial neural network by, for each connection in the set of connections, determining a quantized weight value associated with the connection. Determining the quantized weight value associated with the connection may include (1) associating a loss function with the connection, the loss function including a periodic regularization function that describes a relationship between an input value and a weight value of the connection, (2) determining a minimum of the associated loss function with respect to the weight value in accordance with the periodic regularization function, and (3) generating the quantized weight value associated with the connection based on the determined minimum of the loss function. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for quantizing neural networks via periodic regularization functions

The disclosed method may include (1) determining whether a next operation of a plurality of operations of an artificial neural network (ANN) is dependent upon a Boolean predication value based on a representative value for a weight or an input of a node of the ANN, (2) based on the next operation not being dependent on the Boolean predication value, allowing the next operation to update a state of the ANN, and (3) based on the next operation being dependent on the Boolean predication value, performing at least one of (a) allowing, based on the Boolean predication value being a first value, the next operation to update the state of the ANN, and (b) preventing, based on the Boolean predication value being a second value different from the first value, the next operation from updating the state of the ANN. Various other methods and systems are also disclosed.

Systems and methods for employing predication in computational models

A disclosed computing system may include a special-purpose hardware device having an input subsystem, a linearization subsystem, and a matrix multiplication unit. The input subsystem may facilitate on-the-fly convolution lowering within a neural network convolution layer by directing input volume patches to logical unit(s) of the device. The linearization subsystem may be configured to receive a patch from the input subsystem and to linearize the patch by arranging elements of the patch as a portion of a data matrix row. The matrix multiplication unit of device may be configured to receive the data matrix from the linearization subsystem and to apply a filter matrix to the data matrix via a matrix multiplication operation. Various other methods, systems, and computer-readable media are also disclosed.

Lowering hardware for neural networks

In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular address, address information and count information; and a memory controller to issue read requests to a memory, the memory controller including a locality controller to receive a memory access instruction having a no-locality hint and override the no-locality hint based at least in part on the count information stored in an entry of the sparse access buffer. Other embodiments are described and claimed.

System, apparatus and method for selective enabling of locality-based instruction handling

The disclosed computer-implemented method may include receiving an input value and a floating-point scaling factor and determining (1) an integer scaling factor based on the floating-point scaling factor, (2) a pre-scaling adjustment value representative of a number of places by which to shift a binary representation of the input value prior to a scaling operation, and (3) a post-scaling adjustment value representative of a number of places by which to shift the binary representation of the input value following the scaling operation. The method may further include calculating a scaled result value by (1) shifting rightwards the binary representation of the input value by the pre-scaling adjustment value, (2) scaling the shifted binary representation of the input value by the integer scaling factor, and (3) shifting rightwards the shifted and scaled binary value by the post-scaling adjustment value. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for efficient scaling of quantized integers

The disclosed computer-implemented method may include (i) identifying an artificial neural network that processes each input to the artificial neural network in a fixed number of operations, (ii) performing an analysis on the artificial neural network to determine an execution metric that represents the fixed number of operations performed by the artificial neural network to process each input, (iii) determining a quality-of-service metric for an executing system that executes the artificial neural network, and (iv) optimizing power consumption of the executing system by configuring, based on the execution metric and the quality-of-service metric, a processing throughput of at least one physical processor of the executing system, thereby causing the executing system to execute the artificial neural network at a rate that satisfies the quality-of-service metric while limiting the power consumption of the executing system. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for optimizing power usage for systems within quality-of-service constraints

Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads

The disclosed computer-implemented method for efficiently updating neural networks may include (i) identifying a neural network that comprises sets of interconnected nodes represented at least in part by a plurality of matrices and that is trained on a training computing device and executes on at least one endpoint device, (ii) constraining a training session for the neural network to reduce the size in memory of the difference between the previous values of the matrices prior to the training session and the new values of the matrices after the training session, (iii) creating a delta update for the neural network that describes the difference between the previous values and the new values, and (iv) updating the neural network on the endpoint device to the new state by sending the delta update from the training computing device to the endpoint computing device. Various other methods, systems, and computer-readable media are also disclosed.

Systems and methods for efficiently updating neural networks

Growing community of inventors

Santa Clara, CA, United States of America

Jong Soo Park