Electronics and Telecommunications Research Institute

Jong Son Lyu

Young Min Kim

Bo Woo Kim

Jong Ho Lee

Seong J Kang

Disclosed is a method for manufacturing a metal-oxide-semiconductor (MOS) device formed in an epitaxial silicon layer on insulator substrate comprising the steps of forming a field oxide layer defined an active region of the MOS device in the silicon layer and forming a gate oxide on the silicon layer; forming a gate electrode on the gate oxide, and self-aligned implanting a dopant of low concentration to form a lightly doped drain region; forming an oxide spacer in both sides of the gate electrode; growing a SiGe epitaxial layer having a lower bandgap than the silicon layer on the portion of the exposed silicon layer; and implanting a dopant of high concentration over the SiGe epitaxial layer to form a highly doped source/drain region. This invention can easily manufacture an SOI MOS device having a low source/drain series resistance and a high breakdown voltage without additional complex processes.

Method for making a silicon-on-insulator MOS transistor using a

There is disclosed a method of fabricating BiCMOS semiconductor devices. External metal lines are not used for connecting the NPN bipolar device and NMOS device, or NPN bipolar device and PMOS device. In this case, the collector and base of the bipolar device are respectively in common with the drain and source of the CMOS. The bipolar transistor is in common with the bulk region of the CMOS, so that the diffusion layer is commonly used in the NPN-PMOS pair, and the diffusion layers of the connecting part are connected together in the NPN-PMOS pair. A metal line is connected to the junction of the diffusion layers, thus decreasing the connecting area of the metal line. Hence, the integrability of the chip is increased, and the metal connection causes a reduction of the RC delay time, thus improving the operational speed.

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Daejeon, South Korea

Jong Son Lyu