Samsung Electronics Co., Ltd.

Jong-Sin Yun

Kyung-Woo Kim

A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other. A voltage control unit controls a power voltage to obtain a controlled voltage appliable to the memory cells in response to a control signal that controls an operation of the memory cells. At least one dummy cell is disposed between the voltage control unit and the memory cells and is configured to reduce the controlled voltage to a predetermined level.

Semiconductor memory device and method of operating the same

A semiconductor memory device includes a plurality of word lines, a plurality of pairs of bit lines and complementary bit lines that cross the word lines, and a plurality of memory cells, each memory cell being disposed at a region where a respective word line and a pair of a bit line and a complementary bit line cross each other. A voltage control unit includes a plurality of elements connected in series between a power voltage source and the memory cells and are switched on/off in response to a control signal that controls an operation of the plurality of memory cells. The voltage control unit controls the voltage of the power voltage source to a predetermined level, thereby obtaining a controlled voltage to be supplied to the memory cells.

A semiconductor memory device includes a first memory cell array that comprises first memory cells arranged in a matrix of first rows and first columns; a second memory cell array that comprises second memory cells arranged in a matrix of second rows and second columns; a row decoder that is configured to select and activate one of the rows of the first and second cell arrays in response to a row address; a sense amplifier that may be disposed between the first memory cell array and the second memory cell array; a switch that is configured to selectively connect the sense amplifier to the first memory cell array and the second memory cell array; and a switch controller that is configured to control the switch to connect the sense amplifier to one of the first and second memory cell arrays based on the row address.

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Seoul, South Korea

Jong-Sin Yun