Samsung Electronics Co., Ltd.

Mtekvision Co., Ltd.

Samsung Electro-mechanics Co., Ltd.

Jong-Sik Jeong

Kang-ju Kim

Jae-seong Shim

Byung-jun Kim

Chan-Dong Cho

Keun-woo Park

Won-Tae Choi

Kyoung-Joong Min

Byoung-Won Hwang

Sang-Hyun Park

Yeon-Cheol Lee

Hyung-Man Park

You-Hoan Jung

Boo-Dong Kwak

Yoon-woo Lee

Se-jin Kang

Byoung Won Hwang

Gyu-hwan Jung

Hyun-ll Kim

A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor is mounted on top of the first substrate; a second stacking unit including a second substrate and a plurality of storage devices, wherein the second substrate and the plurality of storage devices are stacked on the second stacking unit, a pattern and a via hole being formed on the second substrate, and the plurality of storage devices are mounted on top of the second substrate; and at least one solder ball arranged on the first stacking unit, the at least one solder ball allowing the first substrate to be coupled to the second substrate.

Multimedia platform

A chip having integrated multiple processor cores and a data processing method are disclosed. The processor chip includes an MP core (main processor core), an AP core (application processor core) which performs a processing function designated by a control of the MP core, a first SM controller which sets a path such that the MP core is coupled with a shared memory, and a second SM controller which sets a path such that the AP core is coupled with the shared memory. By virtue of the present invention, the number of chips installed can be minimized, to allow efficient utilization of PCB space and enable a compact size for a portable terminal.

Chip combined with processor cores and data processing method thereof

The present invention relates to a device having a shared memory and a code data transmitting method. According to an embodiment of the present invention, the digital processing device can include n processors, n being a natural number of 2 or greater; and a shared memory, coupled to each of the processors through independent buses and having a boot section allotted, the boot section being for writing a boot program code to be used for booting of at least one processor.

Device having shared memory and method for transferring code data

A device having a shared memory and a shared memory controlling method are disclosed. A digital processing device can include a shared memory, having a storage area including at least one common section, coupled to each of the processors through separate buses and outputting access information to whether a processor is accessing a common section. With the present invention, each processor can efficiently use or/and control a shared memory by using access information.

Device having shared memory and method for controlling shared memory

A device comprising a multimedia platform with a plurality of memories and a method of sharing a non-volatile memory. The multimedia platform in accordance with an embodiment of the present invention can have a non-volatile memory, a multimedia processor setting a route in accordance with a route selection signal received from the main processor such that the main processor accesses the non-volatile memory or the display unit, a first volatile memory which is a temporary memory device of the main processor, and a second volatile memory which is a temporary memory of the multimedia processor. With the present invention, the portable terminal can be made smaller by putting a memory chip and a multimedia platform in a single chip by use of the POP (package on package) technology.

A method and a device for correcting a code data error are disclosed. A main processor included in a digital processing device in accordance with an embodiment of the present invention writes in a shared memory third code data error-corrected by a predetermined error correcting method or second code data written in a backup area if there is an error in first code data written in a code data area of a nonvolatile memory. The main processor or an application processor performs an operation corresponding to the third code data. With the present invention, a system can be stably operated thanks to promptly dealing with an error when the error in boot codes is detected or generated.

Method and device for correcting code data error

A device having a shared memory and a method for providing access status information by the shared memory are disclosed. A digital processing device includes n processors and a shared memory. The shared memory is coupled to each processor though a separate bus, its storage area includes m common sections, and generates and outputs access status information related to whether an arbitrary processor is accessing at least one of the common sections. With the present invention, a control sequence of each processor can be simplified at a maximum by allowing the shared memory to generate and output access status information related to the common sections.

Device having shared memory and method for providing access status information by shared memory

A method of controlling a shared memory and a user terminal controlling the operation of the shared memory are disclosed. The portable terminal according to an embodiment of the present invention has a memory unit with a storage area partitioned to blocks in a quantity of n and a plurality of processors reading or writing data by accessing a partitioned block. At least one of the partitioned blocks is assigned as a common storage area, accessible by a processor having an access privilege, and the processor having the access privilege performs an operation of maintaining the data stored in the common storage area. With the present invention, the common storage area can be accessed by a plurality of processors, and thus the data transmission time between the processors can be minimized.

Operation control of a shared memory partitioned into multiple storage areas

A portable terminal and a method of controlling a shared memory, the portable terminal are disclosed. The portable terminal includes a memory unit, being equipped with at least 2 ports and having a storage block partitioned into partitioned blocks in a quantity of n, and a plurality of processors, reading or writing data by accessing a particular partitioned block through each dedicated port. At least one of the partitioned blocks is assigned to a common storage block, accessible by a processor having an access privilege, and the access privilege is transferred between the plurality of processors. The common storage block can be partitioned into k sub partitioned blocks, which the data type and process to be stored are predetermined. With the present invention, in the case of the common storage block for the plurality of processors, by allowing the partitioned storage blocks to be partitioned again into sub partitioned blocks depending on a type of data to be stored, the data processing/transmission speed and efficiency can be optimized.

Portable device and method for controlling shared memory in portable device

A device and a method for sharing a memory interface are disclosed. According to preferred embodiments of the present invention, a supplementary control unit included in a digital processor can control some of the pins, constituting a memory interface, to be shared by a plurality of memory. With the present invention, the number of pins included in a memory interface can be minimized, thereby reducing the size of a supplementary control unit, saving the manufacturing cost, and improving the processing efficiency.

Sharing memory interface

A line buffer and a method of providing data to a 3&#xd7;3 line interpolation processor using the line buffer in an image processing system, such as a digital camera, includes a readable and writable single memory, a buffer register having a prior data area storing first line image data, which has been stored in a memory, in a unit of 2m bits, and having a present data area storing second image data, which is inputted from an image sensor in a unit of m bits, in a unit of the 2m bits, and a memory controller providing the memory with a chip enable signal, a write enable signal, and an address indicating locations of the first and second line image data stored in the buffer register, reading and writing the first and second line image data from and on the memory, and outputting the first and second line image data and a third line image data, which is inputted from the image sensor.

Line buffer and method of providing line data for color interpolation

An apparatus for and a method of simultaneously performing edge detection and enhancement without any additional memory storage include an image sensor sensing an image to output image data, a line buffer receiving the image data to output the image data, a register storing the image data transmitted from the line buffer, an interpolation unit performing an interpolation operation on the image data received from the register, an edge detection unit performing an edge detection operation on the image data received from the register to output an edge detection signal in parallel to the interpolation operation of the interpolation unit according to a selection signal representing a pattern of the image data stored in the register, and an edge enhancement unit enhancing an output of the interpolation unit according to the edge detection unit of the edge detection unit.

Apparatus for and method of edge enhancement in image processing

Disclosed herein is a method for processing image data of an optical mouse. In the method for processing image data of an optical mouse, direction and size values of motion vectors which are image data consecutively inputted from an image pixel array are filtered with respect to X and Y axes by a filter. A predetermined number of motion vectors converted by and outputted from the filter are accumulated, and the accumulated values are mapped to conversion values to attenuate noise components and amplify directionality of the motion vectors depending on a speed of the optical mouse by a mapper. The values mapped by the mapper in a plurality of pipes are stored, and a value obtained by adding the plural stored values to each other and dividing the added result value by a conversion factor is transmitted to a personal computer (PC) interface such as a Universal Serial Bus (USB) or PS/2. Accordingly, the present invention is advantageous in that it minimizes noise components of the optical mouse, and consequently ensures the unnatural movement of a cursor on a PC screen.

Method for processing image data of optical mouse

Disclosed herein is a method of processing data of an optical mouse. The method includes the steps of calculating a motion vector of the optical mouse through processing of digitally converted image pixel data in an Image Signal Processor (ISP) by sequentially overlapping a reference image of an n&#x2212;1 th frame to a present image of an nth frame and determining a moving direction of the optical mouse using approximately equal parts in the reference and present images; and transmitting the calculated motion vector to a personal computer through an interface; wherein the ISP includes an X axis navigation engine for processing data on a reference image for the motion of an X axis direction among the processed image pixel data and a Y axis navigation engine for processing data on a reference image for the motion of a Y axis direction among the processed image pixel data.

Method of processing data of optical mouse

Disclosed herein is a single integrated circuit for an optical mouse. The circuit includes an image pixel array for recognizing light and shadow of a surface under the optical mouse, an analog-to-digital converter for receiving analog signal from the image pixel array and converting analog data into digital data, a motion vector calculation unit for converting the digital data into one-bit data and calculating a motion vector, a motion vector process unit for accumulating motion vectors, correcting errors of the motion vectors, and accumulating moving distances of the optical mouse, a timing signal generator for generating control signals to control an overall operation of the circuit and operation signals pursuant to operation states of the circuit, an interface designed to transmit values processed by the process unit into a personal computer, and a transceiver for enabling one of a universal serial bus or an IBM personal system/2 in the interface.

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Seoul, South Korea

Jong-Sik Jeong