Samsung Electronics Co., Ltd.

Jong Shin Shin

Jae Hyun Park

Ji Young Kim

Hyun-Goo Kim

Jun Han Bae

Myoung Bo Kwak

Chi Won Kim

Hyun Su Chae

Jin Ho Han

Seung Hee Yang

An integrated circuit includes a differential signal driver that receives a first signal from a first input terminal, receives a second signal, which is a differential signal of the first signal, from a second input terminal, outputs a first output signal corresponding to the first signal to a first output terminal, and outputs a second output signal corresponding to the second signal to a second output terminal. The integrated circuit further includes a first capacitor unit connected to the first output terminal and controlling a slew rate of the first output signal based on a first capacitance, a second capacitor unit connected to the second output terminal and controlling a slew rate of the second output signal based on a second capacitance, and a phase selection unit that receives the first signal and provides the first signal to the second capacitor unit, and that receives the second signal and provides the second signal to the first capacitor unit, so as to control the slew rates of the first and second output signals.

Integrated circuits for controlling slew rates of signals

A fractional-N phase locked loop is provided. The fractional-N phase locked loop includes a phase adjusting circuit detecting a phase difference between a reference clock signal and a feedback clock signal and outputting a plurality of phase clock signals in response to the detected phase difference, a phase selector selecting and outputting one of the plurality of phase clock signals output from the phase adjusting circuit in response to a phase selection signal, a control circuit generating the phase selection signal by using a sigma-delta modulator operation clock signal, which is generated by dividing the selected phase clock signal by each of N or more different integers (N is an integer more than or equal to 2), and a first divider generating the feedback clock signal by dividing the selected phase clock signal by an integer.

Fractional-N phase locked loop, operation method thereof, and devices having the same

In a data recovery circuit, a sampling circuit is configured to sample data using a plurality of sampling clock signals having different phases relative to one another and to output a plurality of sampled data. A recovery data generation circuit is configured to perform a logic operation on the plurality of sampled data and to generate a plurality of intermediate recovery data according to a result of the logic operation. A recovery circuit is configured to check the plurality of intermediate recovery data for existence of an error and to output intermediate recovery data that is error-free, among the plurality of intermediate recovery data, as recovery data.

Data recovery circuit and operation method thereof

A data receiver device includes a logic unit configured to generate a test pattern signal, receive a test result signal in the test mode, and compare the test pattern signal with the test result signal to perform a test in the test mode. The data receiver further includes a system frequency control circuit configured to multiply a reference clock signal by a multiplication factor received from the logic unit and to output a test clock signal, an output terminal configured to serialize the test pattern signal based on the test clock signal and to output an output signal, and an input terminal configured to recover a data signal and a data clock signal from an input signal based on the output signal, to deserialize the data signal based on the data clock signal, and to output the test result signal to the logic unit.

Data receiver device and test method thereof

A transmission line driver and a serial interface data transmission device including the same are provided. The transmission line driver includes a pre-driver configured to generate and output differential input data signals based on a serial transmission data signal, a differential amplifier configured to receive the differential input data signals and to output differential output data signals, and a common mode controller configured to drive the differential output data signals to a predetermined common mode voltage in an idle mode. Accordingly, power consumption can be reduced and a common mode specification can be supported.

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Yongin-si, South Korea

Jong Shin Shin