Samsung Electronics Co., Ltd.

Jong-shin Shin

Myoung-bo Kwak

Jae-Hyun Park

Sang-Hun Lee

Jin-Ho Kim

Sung-Jun Kim

Tae-jin Kim

Ji-young Kim

Jae-youl Lee

Chi-won Kim

Chang-Kyung Seong

Du-ho Kim

Jin-wook Burm

Ju-hwan Yi

Chi-Won Kim

Kwang-Chun Choi

Hwang-Ho Choi

Byung-Hyun Lim

Chang-zhi Yu

Seung-Hee Yang

Seong-kyun Shin

Dae-wung Lee

Aram Martirosyan

Woon-taek Oh

Hye-Yeon Yang

Jung-myung Choi

Woo-Chul Jung

An integrated circuit includes: a phase-shifted data signal generation circuit configured to generate a plurality of phase-shifted data signals from an input data signal based on at least one phase-shifted clock signal; a synchronization circuit configured to generate a plurality of synchronization data signals by applying the at least one phase-shifted clock signal to the plurality of phase-shifted data signals provided by the phase-shifted data signal generation circuit; and a control signal generation circuit configured to perform logic operations on the plurality of synchronization data signals to generate a phase control signal for controlling a phase of the at least one phase-shifted clock signal, and generate a frequency control signal for controlling a frequency of the at least one phase-shifted clock signal.

Integrated circuit detecting frequency and phase of clock signal and clock and data recovery circuit including the integrated circuit

A hybrid clock data recovery circuit includes a linear phase detector configured to generate a recovered data signal by sampling an input data signal in response to a clock signal, and to generate up and down signals having a pulse width difference that is linearly proportional to a phase difference between the input data signal and the clock signal. An arbiter is configured to generate a bang-bang up signal representing that a phase of the input data signal leads a phase of the clock signal and a bang-bang down signal representing that the phase of the clock signal leads the phase of the input data signal based on the up and down signals. A digital loop filter is configured to generate a digital control code based on the bang-bang up and down signals. A digitally controlled oscillator is configured to generate an oscillating frequency of the clock signal in response to the digital control code, and to adjust the oscillating frequency of the clock signal in response to the up and down signals.

Hybrid clock data recovery circuit and receiver

Provided is a method for driving a SERDES circuit, which may reduce waste of a space of the SERDES circuit. The circuit driving method includes generating a common clock signal from a common phase locked loop (PLL) supplying a clock signal to a serializer/deserializer (SERDES) circuit, distributing the common clock signal to an eye opening monitor and a data transmission lane in the SERDES circuit, and driving the eye opening monitor and the data transmission lane using the common clock signal.

Method for driving SERDES circuit

Provided is a clock data recovery circuit including a phase-frequency detector configured to detect a frequency and phase of a reference clock signal and control a frequency and phase of an internal clock signal based on the detected frequency, a frequency detector configured to detect a frequency of a data signal and, based on the detected frequency of the data signal, adjust the frequency of the internal clock signal; and a phase detector configured to detect a phase of the data signal based on the detected frequency of the data signal and adjust the phase of the internal clock signal. Accordingly, a timing controller that includes the clock data recovery circuit is capable of establishing data communication at high speeds when the system is powered on/off to reduce power consumption. Also, the timing controller does not need to include an additional external clock generation device, and is capable of achieving frequency synchronization using a non-precision clock signal generated in the timing controller.

Clock data recovery circuit, timing controller including the same, and method of driving the timing controller

A transmitting circuit includes a positive differential node, a negative differential node, a voltage mode driver, and a current mode driver. The voltage mode driver generates a first positive differential signal and a first negative differential signal. The voltage mode driver provides the first positive differential signal to the positive differential node and provides the first negative differential signal to the negative differential node. The current mode driver generates a second positive differential signal and a second negative differential signal. The current mode driver provides the second positive differential signal to the positive differential node and provides the second negative differential signal to the negative differential node. A differential signal voltage swing width between the positive differential node and the negative differential node is based at least on the operational state of the current mode driver and/or the voltage mode driver.

Transmitting circuit and transceiver system including the same

A voltage controlled oscillator (VCO) includes an oscillation frequency signal generation circuit and a transconductance control circuit. The oscillation frequency signal generation circuit has a first transconductance and generates a first oscillation frequency signal and a second oscillation frequency signal based on a voltage control signal and a power supply voltage. The first and second oscillation frequency signals are a pair of differential signals. The oscillation frequency signal generation circuit is configured to output the first oscillation frequency signal from a first output node. The oscillation frequency signal generation circuit is configured to output the second oscillation frequency signal from a second output node. The transconductance control circuit is connected to the first and second output nodes and has a second transconductance. The transconductance control circuit is configured to adjust the second transconductance based on a digital control signal.

Voltage controlled oscillator and phase locked loop including the same

A termination circuit for a HDMI transmitter includes a bias unit and a termination resistor unit connected in parallel between a positive transmission pin and a negative transmission pin. The bias unit generates a bias voltage by selecting the higher voltage among a first voltage received through the positive transmission pin and a second voltage received through the negative transmission pin. The termination resistor unit is formed on a well region biased by the bias voltage, and conditionally provides a termination resistance between the positive transmission pin and the negative transmission pin in response to a termination resistor control signal. The termination circuit conditionally provides a termination resistance without a leakage current. The termination resistance may be varied by using an n-bit control code.

High definition multimedia interface (HDMI) apparatus including termination circuit

A transceiver comprises a transmitter that converts a plurality of data components into serial data in response to a first clock signal and transmits the serial data, and a receiver that receives the serial data and converts the serial data into the plurality of data components in response to a second clock signal generated from the serial data. The transmitter adds at least one dummy bit to the serial data at predetermined intervals. The at least one dummy bit includes information regarding a data type of the plurality of data components.

Transceiver having embedded clock interface and method of operating transceiver

A receiver may include a clock and data recovery circuit, a detection circuit and a sampling clock generator. The clock and data recovery circuit may receive first data and sample the first data to generate recovered data in response to a reception sampling clock signal. The detection circuit may detect a frequency difference between a transmission sampling clock signal and the reception sampling clock signal by comparing the first data and the reception sampling clock signal to generate a frequency difference detection signal. The sampling clock generator may generate the reception sampling clock signal based on the frequency difference detection signal and a first reference clock signal. Therefore, a communication system including the receiver may effectively reduce a jitter noise.

Receiver and communication system having the same

A spread-spectrum clock generator includes: a phase interpolator mixing a plurality of clock signals, which differ from each other in phase, and modulating a clock signal resulting from mixing the clock signals; and a controller generating a control signal to generate weights of the plurality of clock signals for modulating the clock signal. The phase interpolator regulates a modulation speed of the clock by adjusting a generation speed of the weights.

Low-jitter spread-spectrum clock generator

Phase-locked loop (PLL) integrated circuits according to embodiments of the invention provide dual feedback control. The first feedback control utilizes a conventional phase locking scheme that passes a feedback clock signal to an input of a phase-frequency detector (PFD). The second feedback control utilizes an automatic frequency calibrator that evaluates a frequency of an output of a voltage-controlled oscillator (VCO) relative to a locked frequency detected during calibration and provides separate calibration control to a charge pump.

Phase-locked loop integrated circuits having dual feedback control

A digitally controlled oscillator includes a ring oscillator, a parallel resistor bank connected to a first terminal of the ring oscillator and having a resistance that varies according to a digital code, and a serial resistor bank connected to a second terminal of the ring oscillator and having a resistance that varies according to the digital code. A frequency of the ring oscillator linearly varies with a variation in the resistance of the parallel resistor bank and the resistance of the serial resistor bank according to the digital code.

Digitally controlled oscillator

A voltage-controlled oscillator includes a voltage regulator, and a delay unit. The voltage regulator independently receives a first oscillation control signal and a second oscillation control signal to provide a regulated voltage signal which is represented by a regular ratio of combination of the first and second oscillation control signals, and the regulated voltage signal is feedback to the voltage regulator. The delay unit generates an output signal having a frequency varying in response to the regulated voltage signal.

Voltage-controlled oscillator, phase-locked loop (PLL) circuit, and clock generator

A semiconductor device, a spread spectrum clock generator and method thereof are provided. The example semiconductor device may include a frequency dividing unit receiving an output signal, generating a first feedback signal and a second feedback signal by dividing a frequency of the received output signal, and a phase offset unit outputting the output signal having a predetermined or desired phase difference with a reference signal in response to the second feedback signal, wherein the second feedback signal having a higher frequency than the first feedback signal. The example spread spectrum clock generator may include a plurality of frequency dividers which are connected in series and a selector selecting and outputting one of a plurality of output signals, each of the plurality of output signals having a different phase difference with respect to a reference signal, in response to at least one output from one or more of the plurality of frequency dividers. The example method may include receiving a reference signal with a first frequency, generating a feedback signal having a second frequency, the second frequency higher than the first frequency and outputting at least one of a sequentially selected set of output signals in response to the generated feedback signal.

Semiconductor device, spread spectrum clock generator and method thereof

A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first and second main input signals having phases opposite to each other, outputs first and second main output signals, and controls slew rates of the first and second main output signals using at least one main control signal. The second buffer buffers first and second sub-input signals having phases opposite to each other, outputs first and sub-output signals, and controls slew rates of the first and second sub-output signals using at least one sub-control signal. The output driver generates first and second output signals having opposite phases using at least two control signals and the output signals of the first and second buffers.

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Anyang-si, South Korea

Jong-shin Shin