Texas Instruments Corporation

Jong Shik Yoon

Amitava Chatterjee

Brian Goodlin

Shaoping Tang

Shirin Siddiqui

Haowen Bu

Alwin J Tsao

Deborah J Riley

Kayvan Sadra

Manuel A Quevedo-Lopez

Brian Edward Hornung

Karen H R Kirmse

Andrew Tae Kim

The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (). The method comprises forming an active area () in a substrate (), wherein the active area () is bounded by an isolation structure (). The method further includes placing at least one stress adjuster () adjacent the active area (), wherein the stress adjuster () is positioned to modify a mobility of a majority carrier within a channel region () of the MOS transistor (). Other embodiments of the present invention include a MOS transistor device () and a process () for constructing an integrated circuit.

Shallow trench isolation stress adjuster for MOS transistor

Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.

Intentional pocket shadowing to compensate for the effects of cross-diffusion in SRAMs

A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.

Method of manufacturing gate sidewalls that avoids recessing

The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure () over a substrate (), the gate structure () having L-shaped sidewall spacers () on opposing sidewalls thereof and placing source/drain implants (or) into the substrate () proximate the gate structure (). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers ().

Method for manufacturing a semiconductor device using a sidewall spacer etchback

The present invention provides, in one embodiment, a method of fabricating a semiconductor device (). In one embodiment, the method includes growing an oxide layerfrom a substrateover a first dopant regionand a second dopant region, implanting a first dopant through the oxide layer, into the substratein the first dopant region, and adjacent a gate structure, and substantially removing the oxide layerfrom the substrate within the second dopant region. Subsequent to the removal of the oxide layerin the second dopant region, a second dopant that is opposite in type to the first dopant is implanted into the substrateand within the second dopant regionand adjacent a gate structure

Semiconductor device having optimized shallow junction geometries and method for fabrication thereof

A method () of forming an isolation structure is disclosed, and includes forming an isolation trench in a semiconductor body () associated with an isolation region, and filling a bottom portion of the isolation trench with an implant masking material (). An angled ion implant is performed into the isolation trench () after having the bottom portion thereof filled with the implant masking material, thereby forming a threshold voltage compensation region in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material ().

Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)

The present invention provides a method for manufacturing a semiconductor device and method for manufacturing an integrated circuit including the semiconductor device. The method for manufacturing a semiconductor device (), among other steps, includes forming a gate structure () over a substrate (), the gate structure () having sidewall spacers (or) on opposing sidewalls thereof and placing source/drain implants () into the substrate () proximate the gate structure (). The method further includes removing at least a portion of the sidewall spacers (or) and annealing the source/drain implants () to form source/drain regions () after removing the at least a portion of the sidewall spacers (or).

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Plano, TX, United States of America

Jong Shik Yoon