Electronics and Telecommunications Research Institute

Jong Seok Han

Sang Man Moh

Suk Han Yoon

Woo Jong Hahn

Yong Seok Choi

Myung-Joon Kim

Kee-Wook Rim

Gil Rok Oh

An Do Ki

The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

System for controlling data transfer protocol with a host bus interface

The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2 (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X&plus; direction, X&minus; direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y&plus; direction, Y&minus; direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z&plus; direction, Z&minus; direction.

Apparatus and method for interconnecting 3-link nodes and parallel processing apparatus using the same

An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.

Apparatus for controlling cache by using dual-port transaction buffers

Growing community of inventors

Taejon, South Korea

Jong Seok Han