Samsung Electronics Co., Ltd.

Jong-sang Lim

Dae-Yoon Shim

Jeong-sang Lee

A pipeline multiplier capable of multiplying 2's complement codes is disclosed. The multiplier operates the multiplication faster than the conventional one by receiving a first predetermined-bit of a multiplier and a second predetermined-bit of multiplicand; producing a multiplier multiplied by sequentially from a least significant bit (LSB) for the times of the second predetermined-bit numbers; logically ORing a most significant bit (MSB) of a preceding partial sum with a MSB of a present partial sum so as to correct the partial sums; and subtracting output of a last partial sum from a value produced by logically NANDing the multiplier and the MSB of the second predetermined-bit of the multiplicand.

Apparatus for multiplying real-time 2's complement code in a digital

A vertical peaking method and the apparatus thereof comprises the steps of selectively passing vertical and horizontal detail information by low-pass filtering a video signal to detect image brightness, subtracting the detected image brightness data signal from a maximum allowable value, and multiplying the signal obtained from the subtraction operation by the vertical peaking signal, adding it to the luminance signal to output the luminance signal vertically peaked according to image brightness. The apparatus accomplishes the steps via hardware, in which the amount of vertical peaking is controlled by the image brightness, so that the vertical peaking of an image is accomplished uniformly.

Vertical peaking method and the apparatus thereof

A circuit for controlling contrast signal is disclosed. The circuit processes contrast signal separately from the original composite video signal and then the pedestal level of the contrast signal is converted to be at zero level. Thereafter, such processed contrast signal is mixed with the original composite video signal. In structure, the contrast control circuit includes: a color/brightness signal separator for separating color signal and brightness signal from said digital composite video signal; a level converter for converting pedestal level of the brightness signal to be at zero level; a gain controller for controlling the output gain of the level converter; a delay controller for delaying the brightness signal output from the color/brightness signal separator; a mixer for mixing the outputs of the delay controller and the gain controller; and an overflow detection and output section for detecting an overflow from the output of said mixer so that if the overflow is detected, the overflow detection value is restricted to a maximum value.

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Suwon, South Korea

Jong-sang Lim