Electronics and Telecommunications Research Institute

Korea Telecom

Jong Ryul Lee

Ook Kim

Kyung Soo Kim

Jong Kee Kwon

Won Chul Song

Chang Jun Oh

Han Jin Cho

Hee Bum Jung

Moon Yang Park

The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.

Low offset automatic frequency tuning circuits for continuous-time filter

There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.

Low pass filter

A double mode modulator, particularly, for a portable telephone, which is adapted to realize both digital and analog modulations and have a low phase noise and a reduced locking time with a device readily integrated in an integrated circuit, including: a frequency synthesizer for synthesizing a particular frequency from an external reference clock signal; a digital modulator for performing a quadrature modulation for an output signal of the frequency synthesizer; and an analog modulator for performing a frequency modulation for the output signal of the frequency synthesizer.

Double mode modulator

The digital logic level conversion circuit is for converting a small sinusoidal signal or an unbalanced digital signal to a balanced digital signal with 50% duty ratio, and includes an input level shift circuit, two differential amplifiers, an RS flip-flop, a charge-pump circuit, and a bias circuit. The input level shift circuit for AC coupling a sinusoidal wave with a small amplitude (with a minimum of 0.4 Vpp) and converting it into a middle logic level. The two differential amplifiers is used as comparators having hysteresis each other, operates inversely, and outputs digital signals into the RS flip-flop; the bias circuit for controlling a driving current of the differential amplifiers; the RS flip-flop for driving the charge-pump circuit by outputting a digital signal upon receiving outputs from the differential amplifiers; and the charge-pump circuit for generating a reference potential level of the differential amplifiers.

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Taejon, South Korea

Jong Ryul Lee