Samsung Electronics Co., Ltd.

Jong-ryeul Kim

Byung-se So

Jung-Joon Lee

Kyung-woo Kang

Bok-moon Kang

A multi in-line module and an electronic component socket for the multi in-line module are provided. One embodiment of a multi in-line memory module includes a printed circuit board having at least two protrusions formed along one edge of the printed circuit board. Each of the protrusions has first and second surfaces for blocks of contact pins. Accordingly, the module can include three or more pin blocks on separate surfaces of the protrusions. The module provides a large number of pins without being significantly larger than a conventional SIMM or DIMM. Alternatively, physical and electrical attachment of multiple circuit boards provides three or more independent pin blocks on the various surfaces of the printed circuit boards. A socket for a module includes dielectric protrusions with two or more gaps between the protrusions and contact pins on side surfaces of the protrusions that are in the gaps. Inserting the protrusions of a multi in-line module into the gaps between the protrusions of the socket creates an electrical connection between contact pins on the module and contact pins of the socket.

Multi in-line memory module and matching electronic component socket

A socket for mounting memory module boards on a printed circuit board (PCB) includes a first socket, a second socket and a third socket. The first socket includes a first socket body that receives a first memory module board, a first clip that connects to a tab of the first memory module board, and a first signal line connected to the first clip and extending outside of the first socket body. The second socket is in an area adjacent to the first socket and includes a second socket body that receives the first and a second memory module boards on opposite sides of the second socket body, two sets of upper socket pins disposed within the second socket body, and two sets of lower socket pins disposed to be opposite to the upper socket pins. The third socket is in an area adjacent to the second socket and includes a third socket body that receives the second memory module board, a second clip that connects to a tab of the second memory module board, and a second signal line connected to the second clip and extending outside of the third socket body.

Socket for mounting memory module boards on a printed circuit board

Integrated circuit memory devices and methods of testing same use a word line selection unit generate address signals to selectively activate word lines of a memory cell array in response to a plurality of first input signals. In addition, a write and read control unit independently generates an operation control signal in response to a second input signal that is used to place the memory cell array into a &ldquo;read mode&rdquo; or a &ldquo;write mode.&rdquo; Because the operation control signal is generated independent from the word line selection unit, a wafer burn-in test write operation can be performed on all memory cells of the memory cell array. Moreover, the independence of the write and read control unit can allow the memory cell array to be enabled for a read operation before initiating the read operation through the word line selection unit thereby avoiding any potential race condition.

Integrated circuit memory devices having an improved wafer burn-in test capability through independent operational control of a memory cell array and related methods of testing same

Data masking is performed for an integrated circuit memory device, by generating a pulse in response to a data masking signal that is received on one of a plurality of data masking pins, equalizing a plurality of groups of input/output line pairs during the pulse and precharging the plurality of groups of input/output line pairs during the pulse. The group of input/output line pairs that correspond to the data masking signal then is precharged after the pulse in response to the data masking signal that is received on the one of the plurality of data masking pins. The input and output line drivers also preferably are deactivated during the pulse and the input and output line drivers, except for the group of input and output line drivers that correspond to the one of the plurality of data masking pins, preferably are activated after the pulse. Accordingly, the input and output line pairs that correspond to data input and output pins to be masked may be precharged during the pulse, and they may be continuously precharged after the pulse. Thus, even though the input and output line pairs may have a large resistance, they can be sufficiently precharged upon masking of write data.

Growing community of inventors

Kyungki-do, South Korea

Jong-ryeul Kim