Samsung Electronics Co., Ltd.

Jong-Pil Son

Chul-woo Park

Seong-Jin Jang

Young-Soo Sohn

Uk-Song Kang

Hoi-ju Chung

Ju-Seop Park

Hong-Sun Hwang

Byung-sik Moon

Kwang-il Park

Sang-Uhn Cha

Hak-soo Yu

Su-a Kim

Hyoung-Joo Kim

Kyo-Min Sohn

Jae-Youn Youn

Doo-young Kim

Sang-Yun Kim

Jung-Hwan Choi

Jung-Bae Lee

Jin-ho Kim

Ho-Young Song

Young-Hyun Jun

Jae-Sung Kim

Joo-sun Choi

Je-Min Ryu

Sung-Min Seo

Hyun-Ho Choi

Gong-Heum Han

Won-Il Bae

Seong-young Seo

Seong-Il O

Jae-Don Lee

Bo-Tak Lim

Su-Yeon Kim

Hyuck-Chai Jung

Min-Kyu Jeong

Sin-Ho Kim

Young-soo Sohn

Seung-Hoon Oh

Cheol-Heui Park

A semiconductor memory device which includes a memory cell array, an error injection register set, a data input buffer, a write data generator, and control logic. The error injection register set stores an error bit set, including at least one error bit, based on a first command. The error bit set is associated with a data set to be written in the memory cell array. The data input buffer stores the data set to be written in the memory cell array based on a second command. The write data generator generates a write data set to be written in the memory cell array based on the data set and the error bit set. The control logic controls the error injection register set and the data input buffer.

Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device.

Word-line timing control in a semiconductor memory device and a memory system including the same

A memory device includes a first memory cell array connected to a first internal data line; a second memory cell array connected to a second internal data line; and a line swap circuit configured to connect the first and second internal data lines with first and second external data lines based on an externally received driving signal. The line swap circuit is configured such that, when the driving signal has a first logic level, the line swap circuit connects the first and second internal data lines with the first and second external data lines, respectively, and when the driving signal has a second, different logic level, the line swap circuit swaps the first and second external data lines so that the first internal data line is connected to the second external data line and the second internal data line is connected to the first external data line.

Memory device including error detection circuit

A method of managing memory includes generating a page pool by aligning a plurality of pages of a memory; when a request to store first data is received, allocating a destination page corresponding to the first data using a page pool; and updating a page table using information about the allocated destination page.

Method and apparatus for managing memory

The memory device includes a memory array, control logic and a recovery circuit. The memory array has a first region configured to store data, a second region configured to store a portion of fail cell information, and a third region configured to store recovery information. The fail cell information identifies failed cells in the first region, and the recovery information is for recovering data stored in the identified failed cells. The control logic is configured to store the fail cell information, to transfer the portion of the fail cell information to the second region of the memory array, and to determine whether to perform a recovery operation based on address information in an access request and the portion of the fail cell information stored in the second region. The access request is a request to access the first region. The recovery circuit is configured to perform the recovery operation.

Memory device capable of quickly repairing fail cell

A semiconductor memory device includes an integrated circuit (IC) chip structure, wherein the IC chip includes a substrate, a memory cell disposed on the substrate, and a local well disposed on the substrate, wherein a conductivity type of the local well is different from a conductivity type of the substrate, a wiring stack structure disposed on the IC chip structure, wherein the wiring stack structure includes a signal transfer pattern connected to the memory cell through a signal interconnector, and a thermal dispersion pattern connected to the local well through a thermal interconnector, and a heat transfer structure connected to the thermal dispersion pattern for transferring heat to the thermal dispersion pattern from a heat source.

Semiconductor memory device and a chip stack package having the same

A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged. The semiconductor memory device includes an error correcting code (ECC) circuit configured to generate parity data based on main data, write a codeword including the main data and the parity data in the memory cell array, read the codeword from a selected memory cell row to generate syndromes, and correct errors in the read codeword on a per symbol basis based on the syndromes. The main data includes first data of a first memory cell of the selected memory cell row and second data of a second memory cell of the selected memory cell row. The first data and the second data are assigned to one symbol of a plurality of symbols, and the first memory cell and the second memory cell are adjacent to each other in the memory cell array.

Semiconductor memory devices, memory systems including the same and method of correcting errors in the same

A memory device includes a memory cell array, a data pattern providing unit, and a write circuit. The memory cell array includes a plurality of memory regions. The data pattern providing unit is configured to provide a predefined data pattern. The write circuit is configured to, when a first write command and an address signal are received from an external device, write the predefined data pattern provided from the data pattern providing unit to a memory region corresponding to the address signal.

Memory device, memory module, and memory system

A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.

Semiconductor memory devices, memory systems including the same and methods of operating the same

Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a 'fail' cell by using an error correction code (ECC) operation, and also repairs the 'fail' cell by using a redundancy repair operation when the &#x2018;fail&#x2019; cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the &#x2018;fail&#x2019; cell, and may also change the size of parity bits regarding the changed codeword.

Memory device for performing error correction code operation and redundancy repair operation

A semiconductor memory device includes a memory cell array and a test circuit. The test circuit reads data stream from the memory cell array, configured to, on comparing bits of each first unit in the data stream, compares corresponding bits in the first units as each second unit and outputs a fail information signal including pass/fail information on the data stream and additional information on the data stream, in a test mode of the semiconductor memory device.

A semiconductor memory device includes a memory cell array and a first buffer. The memory cell array includes a plurality of bank arrays. Each of the plurality of bank arrays includes a plurality of memory cells. The memory cell array and the first buffer are configured for performing a first internal read operation, which represents operations of retrieving first data from a first region of the memory cell array and of storing the first data into the first buffer, based on a first read command and a first read address. The first internal read operation is performed based on a deterministic interface in which the first data is stored into the first buffer within a predetermined first duration after the first read command is received and a generation of a first acknowledgement signal is unnecessary after storing the first data into the first buffer is completed.

Semiconductor memory device and memory system including the same

A memory device having an error notification function includes an error correction code (ECC) engine detecting and correcting an error bit by performing an ECC operation on data of the plurality of memory cells, and an error notifying circuit configured to output an error signal according to the ECC operation. The ECC engine outputs error information corresponding to the error bit corresponding to a particular address corrected by the ECC operation. The error notifying circuit may output the error signal when the particular address is not the same as any one of existing one or more failed addresses.

Memory device having error notification function

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Seongnam-si, South Korea

Jong-Pil Son