Samsung Electronics Co., Ltd.

Jong-Nam Baek

Sangwon Hwang

Sung-Hwan Bae

Sang-Wook Yoo

Dong-Hoon Ham

Sang Hoon Lee

Hyun Seok Kim

Joon-Ho Lee

Joonho Lee

Jae Yong Jeong

Intae Hwang

In-Tae Hwang

Sang-Hoon Lee

Hyun-Seok Kim

Heewon Lee

Jinwook Lee

Hyunkyo Oh

Chanha Kim

Hee-Woong Kang

Su Chang Jeon

Seungkyung Ro

Dae-Jin Kim

Donggi Lee

Seung-Yeon Lee

Sejeong Jang

Kyung-Min Kang

Dongkyu Youn

Sang-Ryong Park

Sung Bin Kim

Jung-Seok Hwang

Oak-Ha Kim

San Song

Sung-Bin Kim

A nonvolatile memory device includes a memory cell array that includes memory blocks, wherein each of the memory blocks includes pages each including memory cells, a row decoder circuit that selects one of the pages from a selected memory block of the memory blocks in a write operation and selects memory cells of a close unit from the selected memory block in a close operation, and a page buffer circuit that writes data into memory cells of a page selected by the row decoder circuit in the write operation and writes dummy data into the memory cells of the close unit selected by the row decoder circuit in the close operation. The close unit includes one or more pages, and, in the close operation, the row decoder circuit adjusts a size of the close unit.

Nonvolatile memory device, storage device including nonvolatile memory device, and method of accessing nonvolatile memory device

A storage device includes a nonvolatile memory device, a buffer memory, a controller and a neuromorphic chip. The neuromorphic chip is configured to generate an access classifier based on the access result information and the access environment information. The controller is configured to perform first accesses to the nonvolatile memory device using the buffer memory and to collects the access result information and the access environment information of the first accesses in the buffer memory. The controller is configured to perform a second access of the nonvolatile memory device using the buffer memory. The controller is configured to obtain a prediction result of access parameters associated with the second access by using access environment information associated with the second access and the access classifier.

Storage device including nonvolatile memory device and access method for nonvolatile memory device

Disclosed is a method of writing data in a storage device including a nonvolatile memory device. The method includes receiving write data with a write request, detecting a number of free blocks, if the detected number of free blocks is less than a threshold value, allocating a log block only in accordance with a sub-block unit, but if the detected number of free blocks is not less than the threshold value, allocating the log block in accordance with one of the sub-block unit and a physical block unit, wherein the sub-block unit is smaller than the physical block unit.

Storage device having nonvolatile memory device and write method

A nonvolatile memory device includes a memory cell array including a selected page including multiple error correction code (ECC) units, and a voltage generation unit configured to generate a read voltage to read data from the selected page. Read voltage levels are set individually for the respective ECC units according to data detection results for each of the ECC units. During a read retry section performed with respect to selected ECC units of the selected page for which read errors have been detected, a re-read operation of the selected ECC units is performed according to the respective read voltage levels set for the selected ECC units.

Non-volatile memory device having adjustable read voltage, memory system comprising same, and method of operating same

A nonvolatile memory device includes an array of nonvolatile memory cells and a plurality of page buffers configured to receive a plurality of pages of data read from the same page in the array using different read voltage conditions. A control circuit is provided, which is electrically coupled to the plurality of page buffers. The control circuit is configured to perform a test operation by driving the plurality of page buffers with control signals that cause generation within the nonvolatile memory device of a string of XOR data bits, which are derived from a comparison of at least two of the multiple pages of data read from the same page of nonvolatile memory cells using the different read voltage conditions. An input/output device is provided, which is configured to output test data derived from the string of XOR data bits to another device located external to the nonvolatile memory device.

Memory system including nonvolatile memory devices which contain multiple page buffers and control logic therein that support varying read voltage level test operations

A memory system, including a flash memory including multiple memory blocks, and a controller configured to erase each of the memory blocks using multiple steps. The controller stores, for each of the memory blocks, metadata indicating which of the multiple steps have been completed, and erases each of the memory blocks based on the stored metadata.

Memory system performing multi-step erase operation based on stored metadata

A memory system includes a flash memory including a block having first sub-blocks and second sub-blocks different from each other, the second sub-blocks including free pages only; and a controller configured to erase the flash memory in units of the sub-blocks, and in a garbage collection operation, the controller is configured to copy data of a valid page of the first sub-blocks to at least one of the second sub-blocks.

Memory system

Disclosed is a storage device which includes a nonvolatile memory device including a memory block a program order of which is adjusted regardless of an arrangement of memory cells, and a memory controller that performs address mapping to replace a bad page of the memory block with a normal page of the memory block.

Storage device including non-volatile memory device and repair method

A method for operating a memory controller capable of controlling a maximum count of a read retry operation is disclosed. The method includes programming a first real time clock (RTC) value indicating a time-of-day when a program operation is performed when the program operation for programming a data to a storage region of a non-volatile memory, obtaining information for the storage region by using the first RTC value read from the non-volatile memory and a second RTC value indicating a time-of-day when a read operation is performed, when the read operation for the data programmed to the storage region is performed, and decreasing a maximum count of a read retry operation by using the information, when the read retry operation is performed for the storage region.

Method for operating memory controller, and memory system including the same

Non-volatile memory, method of operating the same, memory system including the same, and method of operating the system

A method for programming a non-volatile memory device includes: providing a non-volatile memory device including data cells capable of storing N-bit data (N is a natural number) and a monitoring cell capable of monitoring whether the N-bit data has been programmed into the data cells; performing a first programming operation for the data cells while inhibiting programming of the monitoring cell; and performing a second programming operation for the monitoring cell while inhibiting programming of the data cells, wherein the second programming operation is performed differently from the first programming.

Non-volatile memory device and method for programming non-volatile memory device

A semiconductor memory device including a flash memory that includes a page, wherein the page includes a plurality of memory cells connected to even bitlines and odd bitlines of the flash memory, and the memory cells are disposed in a plurality of sectors. The semiconductor memory device also includes a memory controller configured to provide the flash memory with a read address that identifies sectors to be read. The flash memory is configured to determine a sequence of even sensing and odd sensing based on the read address and perform the even sensing and the odd sensing according to the determined sequence. In addition, the flash memory is configured to sense data of at least one identified sector that includes memory cells connected to the even bitlines during the even sensing and sense data of at least one identified sector that includes memory cells connected to the odd bitlines during the odd sensing.

Semiconductor memory device and an operating method thereof

The non-volatile memory device includes a plurality of memory cells. Each of the memory cells is configured to achieve one of a plurality of states, and each of the states represents different multi-bit data. In one embodiment, the method of programming includes simultaneously programming (1) a first memory cell from a first selected state to a second selected state and (2) a second memory cell from a third selected state to a refined third selected state. The refined third selected state has a higher verify voltage than the third selected state.

Non-volatile memory devices and programming methods for the same

A non-volatile memory device includes a cell array including a plurality of memory cells, a page buffer block controlling bitlines of the plurality of memory cells to program the memory cells to a first target state or a second target state, and a control logic configured to skip a verify operation for the memory cells programmed to the first target state and perform a verify operation for the memory cells programmed to the second target state during a second program loop when the memory cells programmed to the first target state are determined to be in a pass condition during a first program loop.

Non-volatile memory device and page buffer circuit thereof

A method of operating a nonvolatile memory device includes; performing a verification operation on memory cells while controlling a verification voltage until the memory cells are verification-passed, controlling a level of a bias voltage to be applied to the memory cells according to a level of the verification voltage when the memory cells are verification-passed, and applying the bias voltage to the memory cells.

Growing community of inventors

Hwaseong-si, South Korea

Jong-Nam Baek