Ams Ag

Austriamicrosystems Ag

Jong Mun Park

Martin Knaipp

Georg Roehrer

Martin Schrems

Eugene G Dierschke

Georg Röhrer

Rainer Minixhofer

Verena Vescoli

Victor Sidorov

Friedrich Peter Leisenberger

Georg Rohrer

The semiconductor photodetector device comprises a substrate of semiconductor material of a first type of electric conductivity, an epitaxial layer of an opposite second type of electric conductivity, a further epitaxial layer of the first type of electric conductivity and photodetectors. The epitaxial layer functions as a shielding layer for charge carriers (e, hgenerated by radiation that is incident from a rear side opposite the photodetectors.

Semiconductor photodetector device with protection against ambient back light

A well of a first type of conductivity is formed in a semiconductor substrate, and wells of a second type of conductivity are formed in the well of the first type of conductivity at a distance from one another. By an implantation of dopants, a doped region of the second type of conductivity is formed in the well of the first type of conductivity between the wells of the second type of conductivity and at a distance from the wells of the second type of conductivity. Source/drain contacts are applied to the wells of the second type of conductivity, and a gate dielectric and a gate electrode are arranged above regions of the well of the first type of conductivity that are located between the wells of the second type of conductivity and the doped region of the second type of conductivity.

Method of producing a symmetric LDMOS transistor

The field effect transistor device comprises a substrate () of semiconductor material, a body well of a first type of electric conductivity in the substrate, a source region in the body well, the source region having an opposite second type of electric conductivity, a source contact () on the source region, a body contact region of the first type of electric conductivity in the body well, a body contact () on the body contact region, and a gate electrode layer () partially overlapping the body well. A portion (*) of the gate electrode layer () is present between the source contact () and the body contact ().

Field effect transistor device with separate source and body contacts and method of producing the device

The symmetric LDMOS transistor comprises a semiconductor substrate (), a well () of a first type of conductivity in the substrate, and wells () of an opposite second type of conductivity. The wells () of the second type of conductivity are arranged at a distance from one another. Source/drain regions () are arranged in the wells of the second type of conductivity. A gate dielectric () is arranged on the substrate, and a gate electrode () on the gate dielectric. A doped region () of the second type of conductivity is arranged between the wells of the second type of conductivity at a distance from the wells. The gate electrode has a gap () above the doped region (), and the gate electrode overlaps regions that are located between the wells () of the second type of conductivity and the doped region ().

Symmetric LDMOS transistor including a well of a first type of conductivity and wells of an opposite second type of conductivity

A semiconductor body () comprises a field-effect transistor (). The field-effect transistor () comprises a drain region () of a first conduction type, a source region () of the first conduction type, a drift region () and a channel region () of a second conduction type which is opposite to the first conduction type. The drift region () comprises at least two stripes () of the first conduction type which extend from the drain region () in a direction towards the source region (). The channel region () is arranged between the drift region () and the source region ().

Field-effect transistor and method for producing a field-effect transistor

The p-channel LDMOS transistor comprises a semiconductor substrate (), an n well () of n-type conductivity in the substrate, and a p well () of p-type conductivity in the n well. A portion of the n well is located under the p well. A drain region () of p-type conductivity is arranged in the p well, and a source region () of p-type conductivity is arranged in the n well. A gate dielectric () is arranged on the substrate, and a gate electrode () is arranged on the gate dielectric. A body contact region () of n-type conductivity is arranged in the n well. A p implant region () is arranged in the n well under the p well in the vicinity of the p well. The p implant region locally compensates n-type dopants of the n well.

P-channel LDMOS transistor and method of producing a p-channel LDMOS transistor

A low cost integration method for a plurality of deep isolation trenches on the same chip is provided. The trenches have an additional n-type or p-type doped region surrounding the trench&#x2014;silicon interface. Providing such variations of doping the trench interface is achieved by using implantation masking layers or doped glass films structured by a simple resist mask. By simple layout variation of the top dimension of the trench various trench depths at the same time can be ensured. Using this method, wider trenches will be deeper and smaller trenches will be shallower.

Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body

A high voltage NMOS transistor is disclosed where the p-doped body is isolated against the p-doped substrate by a DN well having a pinch-off region where the depth of the DN-well is at minimum. By the forming space charge region at raising drain potentials a shielding of the drain potential results because the space charge region touches the field oxide between source and drain at the pinch-off region. An operation at the high side at enhanced voltage levels is possible.

High-voltage transistor with improved high stride performance

An n-conductively doped source region () in a deep p-conducting well (DP), a channel region (), a drift region () formed by a counterdoping region (), preferably below a gate field plate () insulated by a gate field oxide (), and an n-conductively doped drain region () arranged in a deep n-conducting well (DN) are arranged in this order at a top side of a substrate (). A lateral junction () between the deep p-conducting well (DP) and the deep n-conducting well (DN) is present in the drift path () in the vicinity of the drain region () so as to avoid a high voltage drop in the channel region () during the operation of the transistor and to achieve a high threshold voltage and also a high breakdown voltage between source and drain.

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