Skhynix Inc.

Samsung Electronics Co., Ltd.

Hynix Semiconductor Inc.

Samsung Sdi Co., Inc.

Industry-University Cooperation Foundation Hanyang University

Other

Samsung Display Co., Ltd.

Ls Mtron Ltd.

Korea Electric Terminal Co., Ltd.

Sk Hynic Inc.

Medical Tool & Technology, LLC

Shin, Young Kee

Jong-Min Lee

Jongryul Jun

Jung-Bum Lim

Jin-Woong Kim

Hyeong-Ju Na

Jae-Hwang Sim

Eun Ah Kim

Seung-Min Lee

Hoo-Sung Cho

Yong-Joon Choi

Hyongsoo Kim

Jeong-Seok Nam

Jae-Kwan Park

Hyung-Bok Choi

Hyug-rae Cho

Dong-Woo Shin

Hei-soog Kim

Young-ho Lee

Dong-Sik Lee

Jee-Yul Kim

Yeonjin Lee

Jinhyun Shin

Jimin Choi

Jee-Hoon Han

Kang-Sik Kim

Kyong-Min Kim

Gi-Tae Mun

Jun-sung Park

Hoon-Jung Oh

Jang-Hwan Jun

Duk-Rae Lee

Jong-Ryul Jun

Il-Cheol Rho

Dae-Wook Kim

Min Gyu Kim

Jong-Hyun Park

Tae-Yong Kim

Yong-Hoon Son

Jaeho Kim

Jae-Han Lee

Jiwon Kim

Young-Woo Park

Min-Woo Song

Jung-Hoon Han

Sang-Hun Jeon

Seong-Ho Kim

Seung-Ho Park

Jae-hong Park

Young Kee Shin

Sun-Kyu Son

Joonsung Kim

Kyoung-Mook Lim

Dong-Sub Kim

Jang-Hyun Kim

Sukkang Sung

Joon Sung Kim

Ok-Kwon Shin

Euntaek Jung

Chul-Hwan Lee

Jang-Hyun You

Yoon-suk Choi

Young-Il Ban

Juik Lee

Seh-woong Jeong

Jeon Il Lee

Dong-Hwa Kwak

Jung-su Han

Jihoon Chang

Jin-hyun Shin

Dong-Sauk Kim

Jun-ki Lee

Suk Kang Sung

Kee-jeong Rho

Ho-Jun Seong

Min-Yong Lee

Byoung-Sung You

Hae-Chul Lee

Ho Chul Yoon

Hyo-Seok Na

Ji-Hye Yang

Christopher Paradies

Jin-Yeon Won

Young-Duk Kim

Sung-won Park

Sung-Chan Lee

Il-Young Kwon

Jae-Hoon Woo

Young-San Kim

Won-Min Kim

Kwang-Su Kim

Chung-Hyo Jung

Jong-Hoon Na

Chul-Jin Jang

Sangdon Lee

Sea-Young Lee

Hae-Jung Yang

Seung-Joo Lee

Jae-ho Ahn

Beom-Rae Jeong

Seong-Jae Min

A semiconductor device includes an electrode structure including electrodes stacked on a substrate and an insulating pattern on an uppermost electrode of the electrodes, a vertical structure that penetrates the electrode structure and is connected to the substrate, a first insulating layer on the electrode and the vertical structure, a conductive pattern that penetrates the first insulating layer and is connected to the vertical structure, an upper horizontal electrode on the conductive pattern, and an upper semiconductor pattern that penetrates the upper horizontal electrode and is connected to the conductive pattern. The conductive pattern has a first side surface on the vertical structure and a second side surface on the insulating pattern.

Semiconductor device including separate upper channel structures and electronic system including the same

A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

Semiconductor memory device, method for fabricating the same and electronic system including the same

A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.

Semiconductor device

A data processing system includes a memory system including a memory device storing data and a controller performing a data program operation or a data read operation with the memory device, and a host suitable for requesting the data program operation or the data read operation from the memory system. The controller can perform a serial communication to control a memory which is arranged outside the memory system and engaged with the host.

Data processing system allocating memory area in host as extension of memory and operating method thereof

A memory system includes a memory device having a plurality of memory blocks for storing data, and a controller configured to perform an erase operation including plural unit erase operations to erase data stored in at least one target memory block included in the plurality of memory blocks. The controller can be configured to perform at least some of the plural unit erase operations onto the at least one target memory block before the at least one target memory block allocated for storing data.

Apparatus and method for erasing data programmed in a non-volatile memory block in a memory system multiple times

A memory system includes a memory device and a controller suitable for controlling the memory device based on read counts for a plurality of pages of the memory device, wherein the controller counts at least one of the read counts in response to a read request, determines whether there is a page whose read count is initialized at every check-pointing period to generate a determination result, and controls the memory device to update the read counts based on the determination result.

Memory system and operating method thereof

A memory system includes a memory device including a plurality of memory blocks, each block having a plurality of pages to store data; and a controller suitable for: selecting error-prone pages each having a number of errors, which exceeds a threshold, among the plurality of pages, based on the number of errors of each of the plurality of pages; ranking the error-prone pages based on the numbers of errors therein; and performing a test read operation on the error-prone pages based on the ranking.

Memory system, data processing system and operation method of the same

A memory system includes a memory device including a plurality of memory blocks, each including a plurality of memory cells coupled to a plurality of word lines, and a controller configured to determine an operation status regarding a selected memory block among the plurality of memory blocks by performing read test operations to the selected memory block in stages. During the read test operations, the controller adjusts the numbers of word lines selected in each of the stages, based on an error.

Apparatus and method for checking an operation status of a memory device in a memory system

A method for performing a sudden power-off recovery operation of a controller controlling a memory device, the method includes: obtaining open block information for open blocks of the memory device and read counts for the open blocks; updating each of the read counts by adding a set value to each of the read counts; storing the updated read counts in the memory device; sequentially reading pages in each of the open blocks without updating the read counts for the open blocks, based on the open block information, to detect a boundary page after the storing of the updated read counts in the memory device; and controlling the memory device to program dummy data in the detected boundary page.

Controller and operation method thereof for managing read count information of memory block

Apparatus and method for erasing data programmed in a non-volatile memory block in a memory system

A capacitor structure includes a plurality of bottom electrodes horizontally spaced apart from each other, a support structure covering sidewalls of the bottom electrodes, a top electrode surrounding the support structure and the bottom electrodes, and a dielectric layer interposed between the support structure and the top electrode, and between the top electrode and each of the bottom electrodes. An uppermost surface of the support structure is positioned at a higher level than an uppermost surface of each of the bottom electrodes.

Capacitor structure and semiconductor device including the same

An apparatus for controlling an operation in a memory system includes a volatile memory including plural memory cells, a column data checking circuitry configured to determine whether all pieces of data outputted from memory cells corresponding to a bit line are identical to each other, and an error correction circuitry configured to determine whether the pieces of data include an error based at least on a type of data, a state of data, and an output of the column data checking circuitry, and to resolve the error.

Apparatus and method for handling error in volatile memory of memory system based on a type of data and a state of data

Semiconductor packages may include a semiconductor chip on a substrate and an under-fill layer between the semiconductor chip and the substrate. The semiconductor chip may include a semiconductor substrate including first and second regions, and an interlayer dielectric layer that may cover the semiconductor substrate and may include connection lines. First conductive pads may be on the first region and may be electrically connected to some of the connection lines. Second conductive pads may be on the second region and may be electrically isolated from all of the connection lines. The semiconductor chip may also include a passivation layer that may cover the interlayer dielectric layer and may include holes that may expose the first and second conductive pads, respectively. On the second region, the under-fill layer may include a portion that may be in one of the first holes and contact one of the second conductive pads.

Semiconductor packages

Growing community of inventors

Seoul, South Korea

Jong-Min Lee