Samsung Electronics Co., Ltd.

Jong Mil Youn

Sung Min Kim

Deok Han Bae

Myung Yoon Um

Gyu C Kim

Ju Hun Park

A semiconductor device is provided. The semiconductor device includes a substrate comprising an element isolation region and an active region defined by the element isolation region, a fin-type pattern on the active region, the fin-type pattern extending in a first horizontal direction, a gate electrode on the fin-type pattern, the gate electrode extending in a second horizontal direction that crosses the first horizontal direction, a capping pattern on the gate electrode, a source/drain region on at least one side of the gate electrode, a source/drain contact on the source/drain region and electrically connected to the source/drain region, and a filling insulating layer on the source/drain contact, the filling insulating layer having a top surface at a same level as a top surface of the capping pattern, and including a material containing a carbon (C) atom.

Semiconductor device and method for fabricating the same

The present invention relates to a method for manufacturing BiCMOS device. The emitter of bipolar transistor and the load resistors of CMOS transistors are formed in such a manner that the amorphous silicon layer is formed at a low temperature in order to prevent an oxide layer from forming on the exposed base region and then the ion impurities are implanted into this region so as to be annealed and oxidized, where the ion impurities are not implanted into the load resistor portion. Thus, any oxide layer is scarcely formed between the emitter region and polysilicon layers. And the resistance becomes substantially low since the amorphous silicon layer is changed to the polysilicon layer with large grains and the emitter region is formed by diffusing the ion impurities. In addition, the polysilicon layer for the load resistors of CMOS transistors is intrinsic and has large grain, thereby making the resistance value high. Accordingly, the present invention can improve the operating speed by the low emitter resistance of the bipolar transistor and can minimize the power consumption by the reduction of the leakage current due to the high load resistance of the CMOS transistors.

Growing community of inventors

Yongin-si, South Korea

Jong Mil Youn