Samsung Electronics Co., Ltd.

Jong-Kyu Ryu

Min-Su Kim

Dae-Seong Lee

Yong-Geol Kim

Ah-Reum Kim

Hyun-chul Hwang

An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Integrated circuit including asymmetric ending cells and system-on-chip including the same

A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Semiconductor devices, methods of designing layouts of semiconductor devices and methods of fabricating semiconductor devices

An integrated circuit includes a semiconductor substrate, first through third power rails, first through third selection gate lines, and a row connection wiring. The first through third power rails on the semiconductor substrate extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through third selection gate lines on the semiconductor substrate extend in the second direction over a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail, and are arranged sequentially in the first direction. The row connection wiring on the semiconductor substrate extends in the first direction to connect the first selection gate line and the third selection gate line.

Integrated circuit including multi-height standard cell and method of designing the same

A sequential circuit includes a first gate circuit, a second gate circuit and an output circuit. The first circuit generates a first signal based on an input signal, an input clock signal and a second signal. The second circuit generates an internal clock signal by performing a NOR operation on the first signal and an inversion clock signal which is inverted from the input clock signal, and generates the second signal based on the internal clock signal and the input signal. The output circuit generates an output signal based on the second signal. Operation speed of the sequential circuit and the integrated circuit including the same may be increased by increasing the negative setup time reflecting a transition of the input signal after a transition of the input clock signal, through mutual controls between the first circuit and the second circuit.

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Seoul, South Korea

Jong-Kyu Ryu