Unitest Inc.

Unitest Incorporation

Jong Koo Kang

Sun Whan Kim

A tester for testing a semiconductor device is disclosed. In accordance with the tester of the present invention, the tester is configured to have different drive signal path and input/output signal path wherein the drive signal path has a fly-by structure, i.e. a daisy chain structure and the input/output signal path has a star-stub structure such that more DUTs may be tested simultaneously and an integrity of the signals is secured.

Tester for testing semiconductor device

A tester for testing a semiconductor device is disclosed. The tester for testing the semiconductor device employs a data selector for converting a logical test pattern data transmitted from a pattern generator into a physical test pattern data and an expected data based on the logical test pattern data, thereby generating various timings based on a time delay instead of using a plurality of clocks to improve a test efficiency and reduce a manufacturing cost.

A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.

Method for calibrating semiconductor device tester

Disclosed herein is a semiconductor test apparatus for simultaneously testing a plurality of semiconductor devices. The semiconductor test apparatus includes a plurality of pattern generation boards, a DUT board, a backplane board, and a power supply unit.

Semiconductor test apparatus for simultaneously testing plurality of semiconductor devices

Disclosed is a memory application tester for testing a semiconductor memory device. A plurality of motherboards of the tester are vertically mounted and connected to memory devices to be tested mounted on an interface board via a HiFix board so that a memory application tester may test more memory device simultaneously, and a limit in the trace length due to the integration of the motherboards is effectively solved.

Memory application tester having vertically-mounted motherboard

Disclosed is an algorithm pattern generator for testing a memory device. It has a configuration which can optimize a configuration of a memory tester including an address scrambling and a data scrambling in the memory tester for carrying out a test at a memory device module level or a component level.

Growing community of inventors

Suwon, South Korea

Jong Koo Kang