Samsung Electronics Co., Ltd.

Jong-Keun Jeon

Heui-Seog Kim

Jae-Hong Kim

Yong-Jin Lee

Wha-Su Sin

Heui-seog Kim

Wha-su Sin

Seok-Young Yoon

Dong-Hun Yi

Kee-Seok Kim

Jung-Hyun Park

Chang-Hoon Lee

Hyeck-Jin Jeong

Hyeck-Jin Joung

Soon-Ju Choi

Dae-Sang Chun

Jong-Ung Lee

An image sensor module and an imaging device. An image sensor package includes a plurality of image sensor chips for generating image signals and a lower transparent board over the image sensor chips. An upper transparent board is positioned over the lower transparent board and includes a lens for focusing an external light to the image sensor chips. An adhesion member is interposed between the upper transparent board and the lower transparent board, and thus the upper and lower transparent boards are adhered to each other by the adhesion member such that the lens and the image sensor chips are aligned with each other. A dehumidifying agent is arranged in the adhesion member to absorb moistures from an interior of the image sensor module. Accordingly, the moistures are prevented from being condensed onto the surface of the image sensor module.

Method of manufacturing an image sensor module

Image sensor module having a wafer level chip size package and method of manufacting the same and imaging device including the image sensor module and method of manufacturing the image device

A semiconductor package and a method of manufacturing the package are provided. The semiconductor package comprises: a mounting substrate including a bond finger; at least one semiconductor chip disposed on the mounting substrate, the semiconductor chip including a bonding pad; a first molding member disposed on the mounting substrate so as to cover the bond finger and the bonding pad, the first molding member including an interconnection path disposed inside the first molding member so as to connect the bond finger to the bonding pad; a conductive element disposed in the interconnection path; and a second molding member overlying the first molding member. The interconnection path can be formed by a laser process. The conductive element can be formed by conductive nanoparticles or metal wires.

Semiconductor package and method of manufacturing the semiconductor package

Example embodiments provide tape structures including a base layer, a neutralizing layer and an adhesive layer. The base layer may support an object. The neutralizing layer may be arranged on the base layer. The neutralizing layer may be grounded to neutralize charges between the base layer and the object. The adhesive layer may be arranged on the neutralizing layer. The object may be attached to the adhesive layer. Example embodiments also provide methods of manufacturing the tape structures, methods of separating a wafer, and apparatuses for separating a wafer.

Tape structures, and methods and apparatuses for separating a wafer using the same

A method of processing a semiconductor wafer that has a first surface and a second surface opposite to the first surface. The method includes forming grooves of a predetermined depth on the second surface on which circuit patterns are formed, attaching a first surface of a protective tape to the second surface on which the grooves are formed, attaching a carrier tape to a second surface of the protective tape opposite to the first surface of the protective tape so that the first surface of the semiconductor wafer can be oriented upward, removing the first surface of the semiconductor wafer by a predetermined thickness and dividing the semiconductor wafer into chips by the grooves, and supplying each chip to a die bonder in the state where the first surface of the of the chip is oriented upward. Only one kind of die bonder is needed. A UV-type tape is not required.

Method of processing a semiconductor wafer for manufacture of semiconductor device

A method of forming solder balls may involve forming bumps through wire boding on land patterns of a circuit substrate. Solder cream may be applied to the bumps through screen printing. The solder cream may be melted via reflow to form solder balls in which the bumps are embedded.

Method of forming solder ball, and fabricating method and structure of semiconductor package using the same

A package stack may include a first package and a second package. The first package may have an IC chip with an active surface and a back surface. The active surface may be connected to a first major surface of a first circuit substrate. The second package may include a second IC chip with an active surface and a back surface. The back surface of the second IC chip may be attached to a first major surface of a second circuit substrate and the active surface of the second IC chip may be electrically connected to the first major surface of the second circuit substrate. The first package may be stacked on the second package so that the active surface of the second package may be electrically connected to a second major surface of the first circuit substrate of the first package. A method may involve providing a first package having a first IC chip and a first circuit substrate and providing a second package having a second IC chip and a second circuit substrate. The first and the second packages may be stacked so that the active surface of the second IC may face and be electrically connected to a major surface of the first circuit substrate.

Package stack and manufacturing method thereof

A POGO pin that can measure low frequency products as well as RF products and also have a long life span, and a test socket including the POGO pin are provided. The POGO pin includes a metal plunger formed of a conductive metal so as to electrically contact the semiconductor package, and a rubber contact pin connected with the metal plunger and formed of a conductive rubber so as to electrically contact the test board.

POGO pin and test socket including the same

A semiconductor package comprises a chip having a top surface for chip pads and a bottom surface opposite the top surface. The top and bottom surfaces define side surfaces. The package further includes an adhesive layer provided within a chip-attaching area substantially defined by side surfaces of the chip and attaches a chip to, for example, a substrate having substrate pads. This prevents the contamination of the substrate pads by the adhesive layer. In one embodiment, the adhesive layer has at least one hole formed therethrough to expose a portion of the bottom surface of the chip. The adhesive layer may include at least one passage laterally connecting the hole to the outside. Alternatively, the adhesive layer has a plurality of adhesive parts separately disposed on the semiconductor chip.

Semiconductor package with improved chip attachment and manufacturing method thereof

The present invention relates to an insert block for testing semiconductor devices. The insert block comprises one or more pushers, installed in a block body having a loading space to accommodate a semiconductor device under test, including a first push rod to apply force to one of adjacent sides of the semiconductor device under test and a second push rod to apply force to the other thereof. Accordingly, firm centering of semiconductor devices under test relative to the contact pins of the test socket along the two perpendicular axes (for instance, x and y axes) on the top or bottom surface of the semiconductor device is achieved and leads to the proper interfaces between the external terminals of the semiconductor device under test and the contact pins of the test socket, and thereby improves the quality of connection therebetween.

Growing community of inventors

Cheonan-si, South Korea

Jong-Keun Jeon