Freescale Semiconductor,inc.

Motorola Corporation

Other

Jong-Kai Lin

Jinbang Tang

William H Lytle

Marc Alan Mangrum

Kenneth R Burch

Darrel R Frear

Lawrence N Herr

Ronald V McBean

Robert E Booth

Owen R Fay

Li Li

Henry G Hughes

Craig S Amrine

Treliant Fang

Hang M Liaw

Theodore Gerard Tessier

Yifan Guo

Ravinder K Sharma

Melissa E Grupen-Shemansky

Ravichandran Subrahmanyan

Scott E Lindsey

Naresh C Saha

Keenan L Evans

Steven Markgraf

Chunsheng Zhang

Ananda P De Silva

A shielding structure is provided for shielding a signal path extending between a first layer and a second layer in an electronic device at a transition region with a transition that extends in a first direction and a second direction orthogonal to the first direction. The shielding structure includes a shielding structure portion, which includes a first shielding via in proximity to a first area of the signal path at the transition; a second shielding via in proximity to a second area of the signal path at the transition; and an area metallization electrically coupled to the first shielding via.

Shielding structures for signal paths in electronic devices

Electromagnetic shielding for an integrated circuit packaged device. The method includes forming shielding structures by forming openings in an encapsulated structure. The openings are filled with conductive material that surrounds at least one die. The encapsulated structure may include a plurality of integrated circuit die. A layered redistribution structure is formed on one side of the encapsulated structure.

Method of making an integrated circuit package with shielding via ring structure

Embodiments include shielded multi-layer packages for use with multi-chip modules and the like. A substrate () (e.g., chip carrier) has an adhesive layer (), where electronic components () are attached. An insulating layer () is formed over the plurality of electronic components, and a conductive encapsulant structure () is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry () is formed over, and in electrical communication with, the plurality of electronic components. A shielding via () is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Shielded multi-layer package structures

Electromagnetic shield formation for integrated circuit die package

Methods and structures provide a shielded multi-layer package for use with multi-chip modules and the like. A substrate () (e.g., chip carrier) has an adhesive layer (), where electronic components () are attached. An insulating layer () is formed over the plurality of electronic components, and a conductive encapsulant structure () is formed over the insulating layer. The adhesive layer is detached from the electronic components, and multi-layer circuitry () is formed over, and in electrical communication with, the plurality of electronic components. A shielding via () is formed through the multilayer circuitry such that it contacts the conductive encapsulant.

Methods and apparatus for EMI shielding in multi-chip modules

An exemplary method and apparatus for MEMS device wafer level and/or array packaging comprises inter alia an EM shielding array of dielectric lid elements () sealed to a MEMS device die array () to produce a sealed MEMS device package array (). Disclosed features and specifications may be variously controlled, adapted or otherwise optionally modified to improve hermetic sealing and/or EM shielding for any MEMS device. An exemplary embodiment of the present invention representatively provides for wafer level packaging of RF MEMS switches prior to device singulation.

Wafer level MEMS packaging

A method of manufacturing components includes providing a substrate (,) having a first coefficient of thermal expansion (CTE), having a first surface (,), and supporting a first plurality of interconnects located over the first surface in a first predetermined pattern. The method also includes providing another substrate (,) having a second CTE, having a second surface (,), and supporting a second plurality of interconnects located over the second surface in a second predetermined pattern. The method further includes assembling together the two substrates at a first temperature outside of a temperature range of approximately 25 to 30&deg; C.

Method of manufacturing components and component thereof

A method for connecting substrates includes using an adhesive interposer structure (11) to bond a semiconductor device (26) to a substrate (18). The adhesive interposer structure (11) includes a non-conductive adhesive laminant (12) and conductive adhesive bumps (13). The conductive adhesive bumps (13) provide a conductive path between conductive bumps (27) on the semiconductor device (26) and conductive metal pads (21) located on the substrate (18). In an alternative embodiment, a conductive adhesive material (34) is screen or stencil printed into vias (39) located on a printed circuit board (38) to form conductive adhesive bumps (33). A non-conductive adhesive (52) is then screen or stencil printed onto the printed circuit board (38) adjacent the conductive adhesive bumps (33). A semiconductor die is then connected to the structure.

Method for coupling substrates and structure

A method of forming an electrically conductive polymer bump (22) over an aluminum electrode (21) produces low contact resistance for an interconnect structure (24). Aluminum oxide is first removed from the aluminum electrode (21). Tiron and palladium are subsequently bonded to the fresh surface of the aluminum electrode (21). Finally, the electrically conductive polymer bump (22) is formed over the aluminum electrode (21). The Tiron and palladium improve the electrical contact between the conductive polymer bump (22) and the aluminum electrode (21) thereby reducing the contact resistance. The Tiron also inhibits corrosion of the aluminum electrode (21) and enhances the conductivity by catalytically shrinking the cyanate ester conductive bump.

Method of forming an electrically conductive polymer bump over an

Interconnect bumps are formed on a circuit substrate using printing or dispensing techniques with a wet photoresist layer as a mask. A conductive paste is disposed in openings of a wet photoresist layer. The conductive paste is at least partially cured before the wet photoresist layer is removed. Alternatively, the wet photoresist layer may remain if it is a photo-imagable polyimide.

Method of forming an electrical interconnect

A method for enhancing aluminum nitride includes, in one version, annealing sputtered aluminum nitride in a reducing atmosphere (11), and subsequently annealing the sputtered aluminum nitride in an inert atmosphere (12). A superior aluminum nitride thin film (13) results. The films can withstand exposure to boiling water for times up to twenty minutes and maintain a refractive index, N.sub.f, greater than 2.0, and a preferred crystalline orientation ratio, I(002)/I(102), in excess of 1000.

Method for enhancing aluminum nitride

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Chandler, AZ, United States of America

Jong-Kai Lin