Fairchild Korea Semiconductor Ltd.

Jong-jib Kim

Chang-Ki Jeon

Sung-lyong Kim

Young-suk Choi

Jong-Tae Hwang

Chang-ki Jeon

Min-hwan Kim

Young-Suk Choi

Sung-Iyong Kim

Chang-seong Choi

Min-whan Kim

In one embodiment, a power integrated circuit device is provided. The power integrated circuit device includes a high-side power switch having a high voltage transistor and a low voltage transistor. The high voltage transistor has a gate, a source, and a drain, and is capable of withstanding a high voltage applied to its drain. The low voltage transistor has a gate, a source, and a drain, wherein the drain of the low voltage transistor is connected to the source of the high voltage transistor and the source of the low voltage transistor is connected to the gate of the high voltage transistor, and wherein a control signal is applied to the gate of the low voltage transistor from the power integrated circuit device. The high-side power switch is turned on when a predetermined voltage is applied to the source of the low voltage transistor, a voltage higher than the predetermined voltage is applied to the drain of the high voltage transistor, and a voltage level of the control signal becomes higher than the predetermined voltage by a threshold voltage of the low voltage transistor.

Power integrated circuit device having embedded high-side power switch

In a high voltage integrated circuit, a low voltage region is separated from a high voltage region by a junction termination. A bipolar transistor in the high voltage region is surrounded by an isolation region having a low doping concentration. The use of a low-doped isolation region increases the size of an active region without reduction of a breakdown voltage.

High voltage integrated circuit including bipolar transistor within high voltage island area

A lateral double-diffused MOS (LDMOS) transistor is provided. The LDMOS transistor includes a semiconductor substrateformed of a material having p-conductivity type impurities, a drift region formed of a material having n-conductivity type impurities on the semiconductor substrate, a first buried layerof p-type material and a second buried layerformed of n-type material. Layersandare arranged at the boundary between the semiconductor substrate and the drift region. A first well regionof p-type material contacts the first buried layern-type in a first portionof the drift region. A first source regionconductivity in a predetermined upper region of the first well region, a drain region formed of a material having second conductivity type impurities in a predetermined region of the drift region, the drain region being spaced a predetermined gap apart from the first well region, a third buried layer formed of a material having first conductivity type impurities in a second region of the drift region, the third buried layer being overlapped with a part of an upper portion of the first buried layer, a second well region formed of a material having first conductivity type impurities in the second region of the drift region, the second well region being overlapped with the third buried layer, a second source region formed of a material having second conductivity type impurities in a predetermined upper region of the second well region, a gate insulating layer formed in a first channel region inside the first well region and in a second channel region inside the second well region, a gate electrode formed on the gate insulating layer, a source electrode formed to be electrically connected to the first source region and the second source region, and a drain electrode formed to be electrically connected to the drain region.

Lateral double-diffused MOS transistor having multiple current paths for high breakdown voltage and low on-resistance

A high voltage semiconductor device is provided. The high voltage semiconductor device includes a tow voltage region, a high voltage region, and a high breakdown voltage isolation region. The high voltage region is surrounded by the low voltage region and has corner portions at one side thereof. The high breakdown voltage isolation region has an isolation region for electrically separating the low and high voltage regions from each other and a lateral double diffused metal-oxide-semiconductor (DMOS) transistor for transmitting a signal from the low voltage region to the high voltage region. In particular, a drain region of the lateral DMOS transistor is disposed between the corner portions of the high voltage region, and opposite edges of the corner portions of the high voltage region and drain region of the lateral DMOS transistor are curved.

High voltage semiconductor device having high breakdown voltage isolation region

A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a source structure having a projected portion with a tip-shaped end portion on its center and formed so as to surround a predetermined region of right and left and upper portions of the projected portion. Two drain structures are formed in a predetermined region surrounded by the source structure. Extended drain structures are formed around the drain structures and the extended drain structures function as a channel with a field effect channel between sides of the projected portion of the source structure. Accordingly, since there are no drain structures on the tip of the projected portion of the source structure, although a radius of curvature of the tip of the projected portion is small, a decrease in a breakdown voltage of a device due to the small radius of curvature of the tip of the projected portion can be suppressed. As a result, a power semiconductor device having a small radius of curvature of the source structure and a high breakdown voltage can be provided.

Growing community of inventors

Seoul, South Korea

Jong-jib Kim