Samsung Electronics Co., Ltd.

Jong-hyun Seok

Young-Ho Lee

Do-Hyung Kim

Dohyung Kim

Won-hyung Song

Jeong Hyeon Cho

Gyu Chae Lee

Yong-Jin Kim

Jonghoon Kim

Kyoung-Sun Kim

Hwanwook Park

Kyeongseon Park

Kwangseop Kim

A printed circuit board includes a first electrically conductive reference plane configured to distribute a first reference voltage applied thereto across a surface area of the first reference plane, and a second electrically conductive reference plane extending parallel to the first reference plane, and configured to distribute a second reference voltage applied thereto across a surface area of the second reference plane. A first layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more first signal lines extending adjacent the first reference plane. The first layer is divided into: (i) a first region in which the one or more first signal lines are disposed, (ii) a second region containing an additional plane that is configured to receive a third voltage and has smaller surface area relative to the surface areas of the first and second reference planes, and (iii) a third region containing a dielectric layer. A second layer is provided, which extends between the first reference plane and the second reference plane, and includes one or more second signal lines extending adjacent the second reference plane. The second signal lines have linewidths that vary as a function of whether they are vertically aligned with the first region, the second region, or the third region.

Multi-level printed circuit boards and memory modules including the same

A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

Semiconductor chip module

A semiconductor chip module includes a PCB including first and second faces; a buffer on the first face; a first chip on the first face, and including a first connection terminal and a second connection terminal, a first signal being provided to the first connection terminal, and a second signal being provided to the second connection terminal; a second chip on the second face, and including a third connection terminal to which the first signal is provided, and a fourth connection terminal to which the second signal is provided. The first connection terminal and the third connection terminal receive the first signal from the buffer at the same time. The first connection terminal be is closer to the buffer as compared with the second connection terminal. The third connection terminal is closer to the buffer as compared with the fourth connection terminal.

A semiconductor module includes a printed circuit board including an integrated circuit chip, connecting terminals at an edge of the printed circuit board, and signal lines respectively connecting electrical connection pads of the integrated circuit chip to the connecting terminals. The connecting terminals are plated using via-holes of the printed circuit board respectively connected to the signal lines.

Semiconductor module having a tab pin with no tie bar

A memory module that includes: a printed circuit board having a connecting terminal; memory chips arranged on the printed circuit board; data buffers disposed on a first surface of the printed circuit board and corresponding to the memory chips; and resistance units disposed on a second surface of the printed circuit board and corresponding to the data buffers.

Memory module

A memory module includes a printed circuit board; first memory chips disposed in parallel with a long axis of the printed circuit board along a first column; second memory chips disposed in parallel with the long axis of the printed circuit board along a second column; and passive elements disposed between the first memory chips and the second memory chips, wherein the passive elements are connected between input/output pins of each of the first and second memory chips and tap pins.

Memory module and manufacturing method thereof

A printed circuit board (PCB) includes a substrate body including a circuit wiring layer; tap terminals provided at a surface of the substrate body and in a peripheral region of the substrate body and electrically connected to the circuit wiring layer; and plating wires corresponding to respective tap terminals, each plating wire extending from an end portion of its respective tap terminal toward an edge of the substrate body and having a line width smaller than a line width of the tap terminal. For at least a first tap terminal, the tap terminal shares an edge with an edge of its respective plating wire. A second tap terminal adjacent the first tap terminal is positioned outside a circle having a radius that equals a length of the plating wire and having a center at a point along the shared edge where the plating wire and first tap terminal connect.

Printed circuit board having terminals

A memory module and a layout method of the memory module. The memory module includes memory devices connected to corresponding tabs through corresponding damping resistors formed on a printed circuit board and includes a first signal line group in a first region between the memory devices and the damping resistors and a second signal line group in a second region between the corresponding damping resistors and the connecting terminals.

Growing community of inventors

Seoul, South Korea

Jong-hyun Seok