Samsung Electronics Co., Ltd.

Kia Motors Corporation

Hyundia Motor Company

Unitest Incorporation

Industry-University Cooperation Foundation Hanyang University

Jong-Hyun Kim

Eun-mi Oh

Sang-Jun Park

Chang-Nyun Kim

Chung-Koo Yoon

Hyo Jin Kim

Sun-Ju Kim

Si Woo Kim

Tae-Ho Kim

Hyun-kwon Chung

Hyun-Ho Park

Hong Jin Kim

Kyung-hun Jung

Ho-Sang Sung

Jae Sung Kang

Nam-Sik Jeong

Ho-Jin Park

Jung Been Im

Ho-Chan Cho

Yeon-Ho Kim

Hak-Sung Lee

Sang-Won Kang

Yaxing Li

Jae-Shin Yi

Jeon Hwangbo

Jong-Gu Kang

Sung-Hee You

Seung-Ki Kong

Uk-Jin Yang

In-Hak Na

A method of operating a smart lighting system comprising a first mobile device, a lighting control device and first through nth (n being a positive integer) lighting devices, includes establishing, by the first mobile device, a first wireless connection with the lighting control device; performing, by the lighting control device, a first time synchronization with the first mobile device; providing, by the first mobile device, the lighting control device with a scheduling information representing operation of each of the first through nth lighting devices according to lapse of time; and controlling, by the lighting control device, operation of each of the first through nth lighting devices based on a current time and the scheduling information, wherein the current time is determined based on the time synchronization.

Methods of operation of smart lighting systems

A method for stabilizing an engine clutch control includes transmitting an engine clutch operation start command from a controller to an engine clutch system, the engine clutch system including an engine clutch, detecting a hydraulic pressure generated during the operation of the engine clutch system, carrying out an oil leakage judgment mode using the controller to determine whether the hydraulic pressure is a normal hydraulic pressure where the operation of the engine clutch is available or if the hydraulic pressure an abnormal hydraulic pressure where the operation of the engine clutch is unavailable, and changing an operation mode to an emergency operation mode wherein the operation of the engine clutch is stopped in case of abnormal hydraulic pressure, and carrying out an operation mode change by operating the engine clutch in a case of normal hydraulic pressure, based on a control by the controller.

Method and engine clutch system for stabilizing engine clutch control, and vehicle employing the method and engine clutch system for stabilizing engine clutch control

Storage devices herein include a non-volatile memory and a controller configured to perform a read operation on a physical page of the non-volatile memory in response to a read request on a logical page of the non-volatile memory from a host. The controller may include a mapping manager configured to manage a plurality of logical blocks by a logical unit. The mapping manager may include a unit map table including a correlation between the logical unit and a physical unit corresponding to the logical unit. Additionally, the mapping manager may be configured to change a mapping method according to whether the unit map table includes a physical unit corresponding to a logical unit including a logical page requested by the host. Related user devices and electronic devices are also provided.

Non-volatile memory devices using a mapping manager

The common voltage generator includes an operational amplifier and a plurality of switches. The operational amplifier is configured to amplify a difference between a first voltage and a second voltage and to output the amplified voltage as a common voltage. The plurality of switches are configured to transmit a third voltage and a fourth voltage as a power supply to the operational amplifier in a first voltage output mode and to transmit a fifth voltage and a sixth voltage as a power supply to the operational amplifier in a second voltage output mode.

Common voltage generator, display device including the same, and method thereof

A switching circuit and a DC-DC converter including the same are provided. The switching circuit includes an output terminal, a plurality of input terminals, and a plurality of switches configured to selectively connect the plurality of input terminals to the output terminal. The plurality of switches include a first switch directly connected to the output terminal and a plurality of second switches connecting the plurality of input terminals to the first switch. The first switch is implemented using a high-voltage transistor. Each of the second switches is implemented using a low-voltage transistor. A gate of the high-voltage transistor is at least two times longer than a gate of the low-voltage transistor. The DC-DC converter increases or decreases a signal selected from among a plurality of input signals input through the input terminals by a predetermined voltage level. Most of switches in the switching circuit are implemented using low-voltage transistors, thereby decreasing the area of the switching circuit.

Switching circuit, DC-DC converter and display driver integrated circuit including the same

A test system for a semiconductor device couples the device to the back side of a circuit board, thereby allowing the device to be tested under actual operating conditions while providing adequate clearance around the device to accommodate automatic handling equipment, and also reducing signal delay and distortion. A system in accordance with the present invention includes a circuit board having circuitry adapted to provide an actual operating environment for the semiconductor device, as for example, a low cost mother board for testing memory devices. The device is coupled to the back side of the circuit board through test terminals formed on the back side of the board. An interface board can be used to correct the pin arrangements, which are reversed because they protrude from the back side of the board, and to compensate for the environmental differences caused by use of sockets and additional equipment on the interface board.

Method and apparatus for testing semiconductor devices using the back side of a circuit board

Semiconductor devices are tested under actual operating conditions by interfacing the devices to an actual board-type product, for example, through a test board tat includes a mounting unit such as a socket or pattern of conductive lands that allows the devices being tested to be mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. For example, the interface circuit can include a clock distribution circuit, which utilizes a phase locked loop, and a register circuit to compensate for electrical loading caused by the device mounting unit, and to provide the proper timing margins between clock signals and control signals applied to the semiconductor devices. A power control circuit can be used to manipulate the supply voltage thereby providing a voltage margin screening function.

Method and apparatus for testing semiconductor devices using an actual board-type product

The present invention relates to a test equipment of a chip memory device. A memory pattern test is implemented using a pattern generation substrate in which a processor is designed in an EPLD for thereby implementing a PC test and pattern programming, so that a test evaluated under a PC environment formed of a CPU and chip sets. Two processes of a chip device test and automatic test are performed in one equipment using a generated test pattern. The PC test and automatic test are separated using a high speed switching device which is capable of implementing a conversion without a signal distortion between the signal lines extended from the chip sets and the pattern generation substrate. Therefore, in the present invention, it is possible to enhance a test performance and decrease the test time and error ratio and cost of the products.

PC and ATE integrated chip test equipment

Embodiments of the invention allow semiconductor devices to be tested under actual operating conditions by interfacing the devices to an actual board-type product. The devices are interfaced to the board-type product with a test board that includes a mounting unit such as a socket or pattern of conductive lands that allows the devices to be easily mounted to and removed from the test board with minimal effort and signal degradation. An interface circuit on the test board compensates for environmental differences between the board-type product and the mounting unit. A power control circuit can be used to manipulate the supply voltage applied to the semiconductor devices, thereby providing a voltage margin screening function.

A multi-bit data block testing circuit and method thereof are described. The semiconductor memory device includes a multi-bit data block testing circuit for testing adjacent cell blocks using any one pattern selected from the same data pattern and a different data pattern during a multi-bit test mode. The multi-bit data block testing circuit further comprises a comparator operatively coupled to receive a data signal from each of the adjacent cell blocks. A multi-bit data block input source is interconnected with the multi-bit data block testing circuit via an input port and provides the data patterns during the multi-test mode. A multi-bit data block output receiver is interconnected with the multi-bit data block testing circuit via an output port and receives a test result indication from the comparator of the multi-bit data block testing circuit.

Multi-bit test circuit and method thereof

Growing community of inventors

Suwon, South Korea

Jong-Hyun Kim