Samsung Electronics Co., Ltd.

Jong Hyun Choi

Jae-Young Lee

Jae Young Lee

Hyong-Ryol Hwang

Sang Seok Kang

Seong Jin Jang

Jin Seok Kwak

Hyang Ja Yang

Kwang Sook Noh

In Cheol Hwang

Jae Hoon Joo

Young Hun Seo

Kwang-Yeol Hwang

Disclosed herein is a motor including a power connector capable of preventing current leakage to the outer case and structural interference with the outer case. The motor includes a stator provided with an insulator, a rotor configured to be rotated against the stator, a power connection portion provided in the insulator, and configured to support an end of a coil wound around the stator and configured to accommodate a mag-mate terminal, and a power connector coupled to the power connection portion to connect an external power source to the coil, wherein the power connector includes a lead wire, a fork terminal coupled to an end of the lead wire to electrically connect the lead wire to the coil and a housing configured to accommodate the end of the lead wire and the fork terminal and coupled to the power connection portion.

Motor

An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device.

Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes

A bit line sense amplifier layout array includes N sense amplifier layout regions, which are arranged adjacent each other and have a sense amplifier, respectively. (N+1&#x2212;i) bit lines and i complementary bit lines are arranged in an isense amplifier layout region among the sense amplifier layout regions. An ibit line among the (N+1&#x2212;i) bit lines and an icomplementary bit line among the i complementary bit lines are connected to a sense amplifier formed in the isense amplifier layout region. The values N and i are natural numbers and i&#x3e;=1 and &#x3c;=N.

Bit line sense amplifier layout array, layout method, and apparatus having the same

A semiconductor memory device is provided. The semiconductor memory device supplies to a sense amplifier a first voltage and a second voltage during data sensing, so that data sensing margin and a data sensing speed increase.

Semiconductor memory device and method of driving the same

The present invention discloses an address buffer and a semiconductor memory device having the address buffer. The address buffer comprises a first buffer for latching a signal in response to a first control signal in a normal operation mode in the semiconductor memory device and generating a buffered signal by buffering the latched signal in response to a second control signal, and a second buffer for maintaining a mode-setting signal in a reset status in the normal operation mode and for outputting the mode-setting signal by using the latched signal in response to the first control signal and a mode-setting command in a mode-setting operation mode. Accordingly, the mode-setting signal is generated only in the mode-setting operation mode, thereby reducing undesirable current consumption.

Address buffer and semiconductor memory device using the same

State change transition times of a semiconductor memory device is reduced by reducing contact resistance associated with unshared input/output (I/O) lines. To minimize the difference in transition times between shared I/O lines having dual precharging circuits and non-shared I/O lines which have only a single precharging circuit, effective contact resistance of the non-shared I/O lines are reduced by eliminating unnecessary isolation gates with their attendant impedances. This provides faster transition times for the non-shared I/O lines.

Growing community of inventors

Suwon-si, South Korea

Jong Hyun Choi