Samsung Electronics Co., Ltd.

Jong-Hyon Ahn

Dong-Hun Lee

You-Seung Jin

Hyuk-Ju Ryu

Soo-cheol Lee

In a method of manufacturing a semiconductor device, a gate insulation layer and a gate electrode are sequentially formed on a substrate on which an active region is defined. A planarized layer is formed on the substrate including the gate electrode. The planarized layer partially removed, and an upper portion of the gate electrode is exposed. A silicon epitaxial layer is selectively formed only on the exposed gate electrode, and the planarized layer is completely removed. A gate spacer is formed along side surfaces of the gate electrode and the silicon epitaxial layer. A source/drain region is formed on a surface portion of the active region corresponding to the gate electrode. Since the silicon epitaxial layer is formed only on the gate region except the source/drain region, the gate resistance is stabilized and the parasitic capacitance between the gate electrode and the source/drain region is reduce.

Method of manufacturing a semiconductor device having a gate structure with low parasitic capacitance

A semiconductor device having a capacitor of an MIM structure and a method of forming the same are described. The semiconductor device includes a semiconductor substrate; a first bottom interconnection formed over the semiconductor substrate; an intermetal dielectric layer formed over the semiconductor substrate; a plurality of openings exposing the first bottom interconnection through the intermetal dielectric layer; a bottom electrode conformally formed on the inside wall of the openings, on the exposed surface of the first bottom interconnection and on the intermetal dielectric layer between the openings; a dielectric layer and an upper electrode sequentially stacked on the bottom electrode; and a first upper interconnection disposed on the upper electrode. According to the present invention, an effective surface area per a unit planar area of a capacitor with an MIM structure is enlarged to increase capacitance thereof.

Semiconductor device having metal-insulator-metal capacitor and fabrication method thereof

A method of fabricating a semiconductor device is provided that includes forming first and second gate electrodes on a substrate via a first photo mask, in which the first and second gate electrodes are in a longitudinal direction parallel to respective channels arranged in x-axis y-axis directions, measuring and comparing the lengths of the first and second gate electrodes on the substrate, estimating a mask bias on the basis of the difference between the actually measured lengths of the gate electrodes, and forming patterns of the first and second gate electrodes of which lengths are adjusted with the estimated mask bias on a new second photo mask, so that the first and second gate electrodes of the same length are formed on the same substrate via the new, second photo mask, regardless of the arrangement directions of the gate electrodes in parallel to channels. This has the effect of improving the processing speed of high CPU or logic element and the yield of products manufactured by this process.

Semiconductor device fabricating method

The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.

Method of making a fuse in a semiconductor device

The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer.

Semiconductor device having a fuse

Method of making a fuse in a semiconductor device and a semiconductor device having a fuse

Method of making a fuse in a semiconductor device and a semiconductor

A method for manufacturing a semiconductor substrate structure wherein a comprising the steps of defining bulk transistor and SOI transistor areas, the bulk transistor area disposed on a lower single crystalline silicon layer, and the SOI transistor area diposed on an upper single crystalline silicon layer. The method characterized in that a spacer is formed on a portion of the bulk transistor area which covers a sidewall of the SOI transistor area, a first conductive well is formed in the lower single crystalline silicon layer and a well oxide layer is formed over the first conductive well region, a second conductive well is formed in the lower single crystalline silicon layer between the SOI transistor layer and the first conductive well, and the first conductive well is rediffused.

Growing community of inventors

Gyeonggi-do, South Korea

Jong-Hyon Ahn