Samsung Electronics Co., Ltd.

Jong-hyon Ahn

Ki-seog Youn

Soo-cheol Lee

Sung-Gun Kang

Hyae-Ryoung Lee

Kong-soo Cheong

Tae-Woong Kang

Jin-Woo Kim

Deok-hyung Lee

You-Seung Jin

Hyuk-Ju Ryu

Kwan-Jong Roh

Chang-hun Lee

Chang-Hun Lee

Ki-Young Kim

Heon-jong Shin

Hee-Sung Kang

Dong-hun Lee

Don-Woo Lee

Sang-don Yi

Jeong-Ho Shin

Do-Yul Yoo

Hye-kyoung Lee

Jin-Won Jun

Su-gon Bae

Jin Hua Liu

Jung-Lim Yoon

Son-jong Wang

Jae-cheol Yoo

Kyoung-mok Son

Young-pill Kim

Moo-jin Jung

Jae-Cheol Yoo

A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.

Trench isolation type semiconductor device which prevents a recess from being formed in a field region and method of fabricating the same

A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.

Semiconductor integrated circuit device and method of manufacturing the same

A MOSFET includes a semiconductor substrate with a first region having a relatively thick first thickness and a second region having a relatively thin second thickness; a gate insulating layer pattern formed on the first region of the semiconductor substrate; a gate conductive layer pattern formed on the gate insulating layer pattern; an epitaxial layer formed on the second region of the semiconductor substrate so as to have a predetermined thickness; spacers formed on sidewalls of the gate conductive layer pattern and part of the surface of the epitaxial layer; a lightly-doped first impurity region formed in the semiconductor substrate disposed below the spacers and in the epitaxial layer; and a heavily-doped second impurity region formed in a portion of the semiconductor substrate, exposed by the spacers.

Method of fabricating a MOSFET having doped epitaxially grown source/drain region on recessed substrate

Provided are a method of fabricating an improved multi-gate transistor and a multi-gate transistor fabricated using the method, in which an active pattern is formed on a substrate, the active pattern having two or more surfaces on which channel regions are to be formed, a gate insulating layer is formed on the channel regions, and a patterned gate electrode is formed on the gate insulating layer while maintaining a shape conformal to the active pattern.

Method of fabricating multi-gate transistor and multi-gate transistor fabricated thereby

A nonvolatile memory device may include a semiconductor substrate; first and second floating gate electrodes formed on the semiconductor substrate; a control gate electrode formed on the first and second floating gate electrodes that may include a line body and a first leg, second leg, and third leg extending vertically from the line body toward the semiconductor substrate; and an inter-layer insulating film interposed between the semiconductor substrate and a lower end of the first leg and between the semiconductor substrate and a lower end of the second leg.

Nonvolatile memory device, method of fabricating and method of operating the same

In a method of fabricating a semiconductor device, a first mask pattern is formed on a substrate. The first mask pattern has a first opening formed to expose the substrate. An oxidation barrier region is formed in the substrate exposed by the first opening, and the first mask pattern is patterned to form a second mask pattern having a second opening. A gate insulation layer is formed on the substrate exposed by the second opening. The gate insulation layer has a variable thickness.

Semiconductor devices and methods of fabricating the same

A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.

Trench isolation type semiconductor device and related method of manufacture

A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.

Non-volatile memory device and methods of manufacturing and operating the same

In an asymmetrical SRAM device, and a method of manufacturing the same, the asymmetrical SRAM device includes a semiconductor substrate on which a plurality of unit cell regions are defined, and a plurality of active regions formed in each of the unit cell regions of the semiconductor substrate, wherein the active regions of each unit cell region are a mirror image of active regions of an adjacent one of the plurality of unit cell regions with respect to a boundary line between the adjacent unit cell regions.

Asymmetrical SRAM device and method of manufacturing the same

In a method of forming a semiconductor device, a copper diffusion-prevention layer is formed underneath a substrate. Impurity regions are formed on the surface of the substrate. A copper wiring is electrically connected to the impurity regions. The copper diffusion-prevention layer is formed before forming the lightly doped source/drain regions to prevent copper atoms from diffusing into the substrate.

Method for manufacturing semiconductor device

In a method of forming a metal gate in a semiconductor device, a gate insulation pattern and a dummy gate pattern are formed on a substrate. An insulation interlayer is formed on the dummy gate pattern to cover the dummy gate pattern. The insulation interlayer is polished such that a top surface of the dummy gate pattern is exposed, and the dummy gate pattern is selectively removed to form a trench on the substrate. A gate spacer is formed on an inner sidewall of the trench for determining a gate length of the metal gate. A metal is deposited to a sufficient thickness to fill the trench to form a metal layer. The metal layer is polished to remain in the trench. Accordingly, the gate length of the metal gate may be reduced no more than the resolution limit of the photolithography exposing system.

Method of forming a metal gate in a semiconductor device

Trench isolation type semiconductor device which prevents a recess from being formed in a field region

An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.

Overlay mark for measuring and correcting alignment errors

A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.

Growing community of inventors

Suwon-si, South Korea

Jong-hyon Ahn