Infineon Technologies Ag

G-link Technology

Qimonda North America Corporation

Qimonda Ag

Infineon Technologies North America Corp.

C-link Technology

Jong-Hoon Oh

Jung Pill Kim

Wayne Frederick Ellis

Oliver Kiehl

Klaus Hummler

George William Alexander

Josef Schnell

Rom-Shen Kao

Jungwon Suh

Lee Ward Collins

Octavian Beldiman

Stephen Charles Bowyer

Ralf Schedel

Young-Seog Kim

A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.

Method and apparatus to reduce power consumption by transferring functionality from memory components to a memory interface

Embodiments of the invention generally provide a method and apparatus for transmitting and receiving clock signals. In one embodiment, the method includes receiving, at a memory device, a first clock signal and a second clock signal. The frequency of the first clock signal may be less than the frequency of the second clock signal. The method further includes performing two or more data access operations using the second clock signal. One of the two or more data access operations may include a read operation and one of the two or more data access operations may include a write operation. The method also includes performing a command processing operation using the first clock signal.

Method and circuit for transmitting a memory clock signal

Embodiments of the invention generally provide a method and apparatus for correcting errors in a memory device. In one embodiment, the method includes receiving a read command and a read address for the read command and reading data from a first location of the memory device corresponding to the read address. The method also includes reading error correction information corresponding to the read address. If the error correction information indicates an error in the data, the error in the data is corrected to produce corrected data and the corrected data is output from the memory device. The corrected data is also written back to a second location in the memory device corresponding to the read address.

Error correction in memory devices

Methods and apparatus that provide an additional level(s) of hierarchy within a bank of a Dynamic Random Access Memory (DRAM) are provided. The bank has a plurality of separately addressable sub-banks.

Semiconductor memory having a bank with sub-banks

A computing system having a plurality of processors including a first processor configured with an address port and a second processor configured with an address port, and a memory device having a first port configured as an address port and to alternatively interface with the address port of the first processor and the address port of the second processor.

System memory device having a dual port

An integrated circuit having a nominal minimum burst length defined by a nominal data prefetch size transfers data by accepting an abbreviated burst data read request directed to a first bank, prefetching less than the nominal data prefetch size, and providing the data in an abbreviated burst data transfer less than the nominal minimum burst length.

Abbreviated burst data transfers for semiconductor memory

One embodiment of the present invention provides a multi-chip package including a logic device providing a clock signal having a frequency and a memory device. The memory device receives the clock signal and operates at the clock signal frequency. The memory device includes a temperature sensor providing a temperature signal indicative of a temperature of the memory device, wherein the logic device adjusts the clock signal frequency bases on the temperature signal.

Multichip package with clock frequency adjustment

Embodiments are provided in which a method and apparatus for accessing a special mode register of a memory device are described. A command to access the special mode register is detected. The command is executed by driving data from the special mode register onto a data bus. The command self-terminates by placing the data bus in a high impedance state. One or more unused address bits may specify one of a plurality of special mode registers to be accessed by the command. The command to access the special mode register may be incapable of changing one or more bits in a mode register.

Technique to read special mode register

A memory includes a first macro chip, a spine chip, and a common substrate. The common substrate is configured to pass signals between the first macro chip and the spine chip. The first macro chip, the spine chip, and the common substrate provide a memory.

Memory configured on a common substrate

Embodiments of the invention provide a method and apparatus for accessing a non-volatile memory controller and a volatile memory via a shared interface. In one embodiment, the method includes selecting one of the non-volatile memory controller and the volatile memory via shared control signals of the shared interface, wherein the shared control signals are issued to the non-volatile memory controller and the volatile memory. The method also includes issuing commands to the selected one of the non-volatile memory controller and the volatile memory via the shared control signals.

Shared interface for components in an embedded system

A device or method for activating a memory, which includes receiving a select signal at the memory, receiving a plurality of address bits at the memory, determining whether the select signal is active, determining whether a first bit in the plurality of address bits has a first value, and activating the memory only if the select is active and the first bit has the first value.

Memory system

A random access memory system has a memory controller, a first memory device, a second memory device, and a memory bus. The memory controller is configured to control access to a plurality of memory devices. The memory bus is configured to alternatively couple the memory controller to the first memory device and to couple the memory controller to the second memory.

Memory system and method of operating memory system

Methods and apparatus that may help reduce standby current in memory devices are provided. By separating equalizing and precharging functions into separate circuit structures, current paths between a source of precharge voltage and a defective wordline (e.g., having an inadvertent short to a bitline due to a manufacturing defect) may be eliminated.

Technique to suppress bitline leakage current

Apparatus and methods for communicating command and address inputs to a memory device. In one embodiment, a memory device includes a shared bus interface defined by a portion of pins from a command bus interface and a portion of pins from an address bus interface. Each portion of pins is configured to receive address and command inputs, depending a given command/address combination being asserted by a memory controller.

Method and apparatus for communicating command and address signals

Embodiments of the invention generally provide a method and wordline driver having a reduced leakage current. In one embodiment, a wordline is driven to a boosted high voltage with a driver transistor of the wordline driver if the wordline driver is in an operational mode and the wordline is driven to a downward-driven low voltage if the wordline driver is in a standby mode. The driver transistor is electrically isolated from the downward-driven low voltage of the wordline when the wordline driver is in the standby mode. A leakage current in the wordline driver is thereby reduced.

Growing community of inventors

Chapel Hill, NC, United States of America

Jong-Hoon Oh