Samsung Electronics Co., Ltd.

Jong-Hoon Nah

Sang-Jin Kim

Jong-Seo Hong

Jung-Woo Seo

Choon-Ho Song

Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

Growing community of inventors

Suwon-si, South Korea

Jong-Hoon Nah