Samsung Electronics Co., Ltd.

Seoul National University

Snu Rdb Foundation

Lg Cable Ltd.

Korea Institute of Science and Technology

Skhynix Inc.

Other

Hyundai Motor Company

Korea Advanced Institute of Science and Technology

Yonsei University

Kyungpook National University Industry-academic Cooperation Foundation

Korea Research Institute of Bioscience and Biotechnology

Chung Ang University Industry Academic Cooperation

Ewha University-industry Collaboration Foundation

Information and Communications University, Research and Industrial Cooperation Group

Jong-Ho Lee

Glenn A Adams

Kwang-kee Lee

Hyung-suk Jung

Nae-in Lee

Joo-Hyun Lee

Sang-Boh Yun

Sung-Soo Hwang

Ha-Jin Lim

Jin-Woo Park

Min-Joo Kim

Ju-Youn Kim

Jong-Hwan Lee

Sung-Hwan Kim

Eun-Chul Ahn

Seok-Jun Won

Si-Young Choi

Hyun-Cheol Park

Kyung-Ho Park

Yong-Ho Ha

Young-Hoon Kwon

Jae-Eun Park

Tai-Su Park

Hye-Lan Lee

Jaewon Kim

Dong-Hyun Kim

Yong-hwan Kwon

Byung-Hee Kim

Tae-Sung Kim

Hwa-Sung Rhee

Tae-Young Oh

Young Woo Park

Sun-Won Kang

Jae-Hak Chung

Seung-Hoon Nam

Ig Jae Kim

Yong Seok Choi

Geum-jong Bae

Jong-Hyeuk Lee

Min Joo Kim

Young-Hun Kim

Cha-Jea Jo

Jae-Youn Youn

Chan-Soo Hwang

Jong-Mil Youn

Jeong-Hyun Kim

Kyung-In Choi

Jong-Joo Lee

Chungyong Lee

Do-Jun Yang

Keon-Kook Lee

Hong-soo Kim

Un-gyo Jung

Sung-Yoon Jung

Hyung-Suk Jung

Yun-Seok Kim

Hae-Weon Lee

U-in Chung

Pyoung-Wan Kim

Ji-Won Son

Soong-Yoon Choi

Young-lyong Kim

Jong-Ho Yang

Dong-Kil Shin

Dae-ho Lee

Seung-Jun Shin

Se-Young Jeong

Jae-Hwan Jeon

Nam-Seog Kim

Jong-Soo Seo

Gab-Jin Nam

Sang Chul Ahn

Jung Jae Yu

Toshiro Nakanishi

Ji Hyun Park

Hong-Soo Kim

Yong-Soo Cho

Chung-Sun Lee

Ho-jun Kim

Jin-Ghoo Choi

Sang-cheon Choi

Hyun-Il Yoo

Koung-min Ryu

Joonhyuk Kang

Gil-Heyun Choi

Jae-Kwang Choi

Sung-Wook Ahn

Sang-Jae Rhee

Jae-Kwon Kim

Seong-Ho Shin

Chul-yong Jang

Seong-Cheol Kim

Hyun-Ick Shin

Dong-Chan Suh

Myeong-Soon Park

Shle-Ge Lee

Sung-wook Byun

Mi Kyung Park

Chan-yong Lee

Eun Namgung

Provided is a 3D synapse device stack, a 3D stackable synapse array using the same, and a method for manufacturing the 3D synapse device stack. The 3D synapse device stack comprises: a body electrode disposed on a substrate in a vertical direction; a plurality of first insulating layers and third oxide layers alternately stacked on the outer circumferential surface of the body electrode; a plurality of semiconductor bodies disposed on an outer circumferential surface of the third oxide layer; a plurality of sources alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a first side surface of the body electrode; a plurality of drains alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a second side surface of the body electrode; a plurality of word lines alternately stacked with first insulating layers on outer circumferential surfaces of the semiconductor bodies positioned on a third side surface of the body electrode; and an insulator stack positioned between the word line and the semiconductor body. The semiconductor body, the source, the drain, the insulator stack and the word line located on the same layer on the outer peripheral surface of the body electrode constitute a synapse device, or a part thereof. The synapse device stack may implement an AND-type or NOR-type synapse array.

3D synapse device stack, 3D stackable synapse array using the 3D synapse device stacks and method of fabricating the stack

A flash memory device includes a cell array and a control circuit. The cell array includes a first NAND string having first flash memory cells having control gates respectively connected to word lines, and a first bit line selection switch connecting the first flash memory cells to a first bit line according to a control of a first string selection line. The control circuit controls a first erase operation for erasing a selected flash memory cell. The control circuit controls a voltage difference between the first bit line and the first string selection line to have a first value for generating gate induced drain leakage (GIDL) at the first bit line selection switch, and controls a voltage of a control gate of the selected flash memory cell and a voltage of a control gate of an unselected flash memory cell to be different from each other.

NAND flash memory device capable of selectively erasing one flash memory cell and operation method thereof

Provided is a complementary sensors-integrated interface circuit and a differential circuit using the same. The complementary sensors-integrated interface circuit includes: a first sensor having a sensing characteristic for a detection target material; and a second sensor having a sensing characteristic complementary to that of the first sensor for the detection target material, wherein the first sensor is composed of an FET-type sensor, the second sensor is composed of an FET-type sensor or a resistor-type sensor, and the first sensor and the second sensor are connected in series. The interface circuit having the above-described configuration increases the change in output voltage, thereby improving the sensing sensitivity. The complementary sensors-integrated interface circuit is characterized in that it serves as an amplification circuit. In addition, a complementary sensors-integrated differential interface circuit uses the aforementioned complementary sensors-integrated interface circuit, thereby serving as a differential amplifier circuit, reducing noise and improving sensitivity.

Interface circuit and differential interface circuit with integrated complementary sensors

Provided is a 3D capacitor stack and a method for manufacturing the same. The 3D capacitor stack comprises: a drain line electrode having a pillar shape provided in a vertical direction on a substrate surface; a plurality of first insulating layers positioned in first region of an outer circumferential surface of the drain line electrode; a plurality of drains positioned in second regions of an outer circumferential surface of the drain line electrode; a plurality of insulator stacks positioned on side surfaces of the drains; and a plurality of word lines positioned on side surfaces of the insulator stacks. The word lines surrounded by the insulator stacks are positioned on the side of the drains, first insulating layers and drains are alternately stacked on the outer circumferential surface of the drain line electrode, and the word lines surrounded by the insulator stacks and the first insulating layers are alternately stacked; the drain, the word line and the insulator stack constitute a capacitor device, and the capacitor devices electrically isolated from each other by the first insulating layers are vertically stacked to form a stack structure.

3D capacitor stack and method of fabricating the stack

Provided is a ferroelectric-based synaptic device and a three-dimensional synaptic device stack using the same. The synaptic device includes a source, a drain, a semiconductor body in which a channel region are formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode. The insulating layer stack includes: a charge trap layer disposed on the channel region of the semiconductor body and is made of a material capable of storing or trapping electric charges; a ferroelectric layer made of a ferroelectric material; and an insulating layer disposed between the charge trap layer and the ferroelectric layer. The synaptic device is characterized in that weight information is volatilely stored in the charge trap layer and non-volatilely stored in the ferroelectric layer.

Ferroelectric-based synaptic device and method of operating the synaptic device, and 3D synaptic device stack using the synaptic devices

Provided is a sensing method of a FET-type sensor using electric charge storage engineering. The sensing method comprises the following steps to improve reactivity and selectivity to a gas to be sensed: (a) applying a preset erase voltage (Erase bias) or program voltage (Program bias) to the control gate according to the type of gas to be sensed to change a threshold voltage of the FET transducer and control the charge at an interface between the passivation layer and the sensing material layer; and (b) in the recovery phase where the gas detection reaction is terminated and the original state is returned, applying a pre-bias greater or less than a read voltage to the control gate according to the type of gas detected, and then applying the read voltage to the drain and the source of the FET transducer to increase the desorption rate of the detected gas.

Method of sensing on a FET-type gas sensor using charge storage engineering effect

A neuromorphic system enabling on-chip training includes: synapse arrays where synapse devices are arranged in a cross-bar shape; a final neuron layer including a forward neuron and a backward neuron and connected to an output terminal of a last synapse array; neuron layers including a forward neuron, a backward neuron, and a memory storing signals used during a weighted value update operation of a neural network and arranged between the remaining synapse arrays except for a first and last synapse arrays; and an error calculation circuit detecting and outputting an error value of a target signal and an output signal of the forward neuron of the final neuron layer. Conductances of the synapse devices represent weighted values of the neural network and are changed by the weighted value update operation. Each synapse device is configured with a flash device, and the neuron layers are implemented with ultra-miniature devices.

On-chip training neuromorphic architecture

A synapse string includes first and second cell strings each having a plurality of memory cell elements connected in series and first switch elements connected to first or second ends of the first and second cell strings, respectively. The memory cell elements of the first cell string and the memory cell elements of the second cell string are in a one-to-one correspondence, and a pair of the memory cell elements being in a one-to-one correspondence has terminals to which a read voltage is applied connected to each other to constitute one synapse morphic element, so that the synapse string includes a plurality of synapse morphic elements connected in series. A synapse string array architecture enables forward propagation and backward propagation by implementing high-density synapse strings, so that the synapse string array architecture can be applied to a neural network capable of inferencing and on-chip learning, along with inference and recognition.

Synapse string array architectures for neural networks

Provided is a binary neural network including: a synapse string array in which multiple synapse strings are sequentially connected. The synapse string includes: first and second cell strings, each including memory cell devices connected in series; and switching devices connected to first ends of two-side ends of the first and second cell strings. The memory cell devices of the first and second cell strings are in one-to-on correspondence to each other, and a pair of the memory cell devices being in one-to-on correspondence to each other have one-side terminals electrically connected to each other to constitute one synapse morphic device. A plurality of the pairs of memory cell devices configured with the first and second cell strings constituting each synapse string constitute a plurality of the synapse morphic devices. The synapse morphic devices of each synapse string are electrically connected to the synapse morphic devices of other synapse strings.

Neural network with synapse string array

Provided is a neuromorphic system using a neuron circuit. The neuromorphic system includes: one or two or more neuron circuits configured to output a firing signal according to signals input from a synapse array; a homeostatic circuit for each neuron circuit; and a global self-controller configured to generate and provide control signals for the neuron circuits by using the firing signal output from the neuron circuits. The neuron circuit includes a neuromorphic device and an output circuit that outputs the firing signal of the neuromorphic device. The global self-controller generates and supplies a reset signal to the neuromorphic device of the fired neuron circuit, and the global self-controller generates and supplies a lateral inhibition signal to the neuromorphic device of the non-fired neuron circuit. The homeostatic circuit alleviates inhibition of other neurons by the neurons with a predominant firing function.

Neuromorphic system

A nonvolatile memory device includes a gate line extending in a first horizontal direction; a gate electrode of a pillar shape extending in a vertical direction from the gate line; a plurality of bit lines and a plurality of source lines extending in parallel in a second horizontal direction perpendicular to the first horizontal direction, the plurality of bit lines and the plurality of source lines being stacked in the vertical direction; and a plurality of cell transistors vertically stacked to surround an outer side surface of the gate electrode between the plurality of bit lines and the plurality of source lines. Each of the cell transistors includes a gate dielectric layer which surrounds the outer side surface of the gate electrode and a channel layer which surrounds an outer side surface of the gate dielectric layer.

Nonvolatile memory device having stacked cell transistors and operating method thereof

Disclosed are a device and method for providing a checking question designed to allow a user to perform the checking study of correct answers or incorrect answers by using the choices of one or more incorrectly answered questions. The device includes: an incorrectly answered question selection unit which selects one or more questions incorrectly answered by a user from among questions provided to the user; a choice extraction unit which extracts correct answers as choices for the respective selected incorrectly answered questions; a checking question generation unit which generates one or more checking questions designed to allow the user to study the incorrectly answered questions by allocating the extracted choices so that the extracted choices become the choices of the checking questions; and a checking study provision unit which provides the study of the incorrectly answered questions by transmitting the generated checking questions to a user terminal.

Device and method for providing studying of incorrectly answered question

Provided is a 3D stacked memory device having a cell region in which memory stacks are arranged on a substrate. Vertical memory stacks and a vertical interconnect structure are provided in the cell region. The vertical interconnect structure includes: a via-hole formed along a vertical direction of the cell region; and a conductive pillar shaped by filling the via-hole with a conductive material. The vertical interconnect structure is configured to interconnect a top electrode of the vertical memory stack and a conductive region of the substrate along the vertical direction. The 3D stacked memory device has a vertical interconnect structure configured with a vertical wiring plug of a conductive material in a cell region, so that it is possible to facilitate the manufacturing process and providing a vertical interconnect between top and bottom electrodes of the stacked memory device or a peripheral circuit of the substrate.

3D stacked memory and vertical interconnect structures for 3D stacked memory

Provided is synapse strings and synapse string arrays. The synapse string includes: first and second cell strings, each having a plurality of memory cell devices connected in series; and first switch devices, each connected to one of two ends of each of the first and second cell strings. The memory cell devices of the first cell string and the memory cell devices of the second cell string are in one-to-one correspondence to each other, and terminals of pairs of the memory cell devices being in one-to-one correspondence to each other are applied with read voltages and electrically connected to each other to constitute one synapse morphic device, so that the synapse string includes a plurality of synapse morphic devices connected in series. The synapse string includes a peripheral circuit and a reference current source for implementing a function of a neuron.

Synapse string and synapse string array for neural networks

Provided are a neuromorphic device and a neuromorphic circuit using the neuromorphic device. The neuromorphic device is configured to include a first semiconductor region formed on a substrate in a wall shape or a dumbbell shape; first, second, third, and fourth doped regions sequentially formed in the first semiconductor region; first and second gate insulating film stacks disposed on the respective side surfaces of the second doped region; first and second gate electrodes respectively disposed on the respective side surfaces of the second doped region; the first and second gate electrodes disposed on the respective side surface of the second doped region, the first and second gate electrodes being electrically insulated from the second doped, region by the first and second gate insulating film stacks; and first and second electrodes electrically connected to the first and fourth doped regions, respectively.

Neuromorphic devices and circuits

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Seoul, South Korea

Jong-Ho Lee